8 log = logging.getLogger(
'jit_x86')
9 hnd = logging.StreamHandler()
10 hnd.setFormatter(logging.Formatter(
"[%(levelname)s]: %(message)s"))
12 log.setLevel(logging.CRITICAL)
17 sp = asmbloc.asm_symbol_pool()
18 jitter.__init__(self,
ir_x86_16(sp), *args, **kwargs)
19 self.vm.set_little_endian()
20 self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP
21 self.ir_arch.do_stk_segm =
False
29 self.cpu.SP -= self.ir_arch.sp.size / 8
30 self.vm.set_mem(self.cpu.SP,
pck16(v))
33 x =
upck16(self.vm.get_mem(self.cpu.SP, self.ir_arch.sp.size / 8))
34 self.cpu.SP += self.ir_arch.sp.size / 8
38 x =
upck16(self.vm.get_mem(self.cpu.SP + 4 * n, 4))
42 jitter.init_run(self, *args, **kwargs)
49 sp = asmbloc.asm_symbol_pool()
50 jitter.__init__(self,
ir_x86_32(sp), *args, **kwargs)
51 self.vm.set_little_endian()
52 self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP
53 self.ir_arch.do_stk_segm =
False
62 self.cpu.ESP -= self.ir_arch.sp.size / 8
63 self.vm.set_mem(self.cpu.ESP,
pck32(v))
66 x =
upck32(self.vm.get_mem(self.cpu.ESP, self.ir_arch.sp.size / 8))
67 self.cpu.ESP += self.ir_arch.sp.size / 8
71 x =
upck32(self.vm.get_mem(self.cpu.ESP + 4 * n, 4))
84 self.cpu.EIP = ret_addr
85 if ret_value1
is not None:
86 self.cpu.EAX = ret_value1
87 if ret_value2
is not None:
88 self.cpu.EDX = ret_value2
98 self.cpu.EIP = ret_addr
99 self.cpu.EAX = ret_value
102 jitter.init_run(self, *args, **kwargs)
103 self.cpu.EIP = self.
pc
109 sp = asmbloc.asm_symbol_pool()
110 jitter.__init__(self,
ir_x86_64(sp), *args, **kwargs)
111 self.vm.set_little_endian()
112 self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP
113 self.ir_arch.do_stk_segm =
False
122 self.cpu.RSP -= self.ir_arch.sp.size / 8
123 self.vm.set_mem(self.cpu.RSP,
pck64(v))
126 x =
upck64(self.vm.get_mem(self.cpu.RSP, self.ir_arch.sp.size / 8))
127 self.cpu.RSP += self.ir_arch.sp.size / 8
131 x =
upck64(self.vm.get_mem(self.cpu.RSP + 8 * n, 8))
136 args_regs = [
'RCX',
'RDX',
'R8',
'R9']
139 for i
in xrange(min(n_args, 4)):
140 args.append(self.cpu.get_gpreg()[args_regs[i]])
141 for i
in xrange(max(0, n_args - 4)):
146 self.
pc = self.cpu.RIP = ret_addr
147 if ret_value
is not None:
148 self.cpu.RAX = ret_value
153 args_regs = [
'RCX',
'RDX',
'R8',
'R9']
156 for i
in xrange(min(n_args, 4)):
157 args.append(self.cpu.get_gpreg()[args_regs[i]])
158 for i
in xrange(max(0, n_args - 4)):
163 self.
pc = self.cpu.RIP = ret_addr
164 if ret_value
is not None:
165 self.cpu.RAX = ret_value
169 jitter.init_run(self, *args, **kwargs)
170 self.cpu.RIP = self.
pc
orig_irbloc_fix_regs_for_mode
orig_irbloc_fix_regs_for_mode
orig_irbloc_fix_regs_for_mode
def ir_archbloc_fix_regs_for_mode
def ir_archbloc_fix_regs_for_mode
def ir_archbloc_fix_regs_for_mode