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miasm2.arch.ppc.regs module

rom miasm2.expression.expression import *
rom miasm2.core.cpu import gen_reg, gen_regs
xception_flags = ExprId('exception_flags', 32)
pr_access = ExprId('spr_access', 32)
eserve = ExprId('reserve', 1)
eserve_address = ExprId('reserve_address', 32)
PR_ACCESS_IS_WRITE = 0x80000000
PR_ACCESS_SPR_MASK = 0x000003FF
PR_ACCESS_SPR_OFF  = 0
PR_ACCESS_GPR_MASK = 0x0001F000
PR_ACCESS_GPR_OFF  = 12
pregs_str = ["R%d" % i for i in xrange(32)]
pregs_expr, gpregs_init, gpregs = gen_regs(gpregs_str, globals(), 32)
rfregs_str = ["CR%d" % i for i in xrange(8)]
rfregs_expr, crfregs_init, crfregs = gen_regs(crfregs_str, globals(), 4)
rfbitregs_str = ["CR%d_%s" % (i, flag) for i in xrange(8)
                 for flag in ['LT', 'GT', 'EQ', 'SO'] ]
rfbitregs_expr, crfbitregs_init, crfbitregs = gen_regs(crfbitregs_str,
                                                       globals(), 1)
erbitregs_str = ["XER_%s" % field for field in ['SO', 'OV', 'CA'] ]
erbitregs_expr, xerbitregs_init, xerbitregs = gen_regs(xerbitregs_str,
                                                       globals(), 1)
erbcreg_str = ["XER_BC"]
erbcreg_expr, xerbcreg_init, xerbcreg = gen_regs(xerbcreg_str,
                                                 globals(), 7)
therregs_str = ["PC", "CTR", "LR" ]
therregs_expr, otherregs_init, otherregs = gen_regs(otherregs_str,
                                                    globals(), 32)
uperregs_str = (["SPRG%d" % i for i in xrange(4)] +
                ["SRR%d" % i for i in xrange(2)] +
                ["DAR", "DSISR", "MSR", "PIR", "PVR",
                 "DEC", "TBL", "TBU"])
uperregs_expr, superregs_init, superregs = gen_regs(superregs_str,
                                                    globals(), 32)
egs_flt_expr = []
ll_regs_ids = (gpregs_expr + crfbitregs_expr + xerbitregs_expr +
               xerbcreg_expr + otherregs_expr + superregs_expr +
               [ exception_flags, spr_access, reserve, reserve_address ])
ll_regs_ids_byname = dict([(x.name, x) for x in all_regs_ids])
ll_regs_ids_init = [ExprId("%s_init" % x.name, x.size) for x in all_regs_ids]
ll_regs_ids_no_alias = all_regs_ids[:]
egs_init = {}
or i, r in enumerate(all_regs_ids):
   regs_init[r] = all_regs_ids_init[i]

Module variables

var EXPRAFF

var EXPRCOMPOSE

var EXPRCOND

var EXPRID

var EXPRINT

var EXPRLOC

var EXPRMEM

var EXPROP

var EXPRSLICE

var EXPR_ORDER_DICT

var PRIORITY_MAX

var SPR_ACCESS_GPR_MASK

var SPR_ACCESS_GPR_OFF

var SPR_ACCESS_IS_WRITE

var SPR_ACCESS_SPR_MASK

var SPR_ACCESS_SPR_OFF

var TOK_EQUAL

var TOK_INF

var TOK_INF_EQUAL

var TOK_INF_EQUAL_SIGNED

var TOK_INF_EQUAL_UNSIGNED

var TOK_INF_SIGNED

var TOK_INF_UNSIGNED

var TOK_POS

var TOK_POS_STRICT

var all_regs_ids

var all_regs_ids_byname

var all_regs_ids_init

var all_regs_ids_no_alias

var crfbitregs_expr

var crfbitregs_init

var crfbitregs_str

var crfregs_expr

var crfregs_init

var crfregs_str

var exception_flags

var field

var flag

var gpregs_expr

var gpregs_init

var gpregs_str

var i

var mod_size2uint

var otherregs_expr

var otherregs_init

var otherregs_str

var priorities

var priorities_list

var regs_flt_expr

var regs_init

var reserve

var reserve_address

var size_to_IEEE754_info

var spr_access

var superregs_expr

var superregs_init

var superregs_str

var xerbcreg_expr

var xerbcreg_init

var xerbcreg_str

var xerbitregs_expr

var xerbitregs_init

var xerbitregs_str