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arch.py
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1 #!/usr/bin/env python
2 #-*- coding:utf-8 -*-
3 
4 import re
6 from pyparsing import *
7 from miasm2.core.cpu import *
8 from collections import defaultdict
9 import miasm2.arch.x86.regs as regs_module
10 from miasm2.arch.x86.regs import *
11 from miasm2.core.asmbloc import asm_label
12 
13 log = logging.getLogger("x86_arch")
14 console_handler = logging.StreamHandler()
15 console_handler.setFormatter(logging.Formatter("%(levelname)-5s: %(message)s"))
16 log.addHandler(console_handler)
17 log.setLevel(logging.WARN)
18 
19 conditional_branch = ["JO", "JNO", "JB", "JAE",
20  "JZ", "JNZ", "JBE", "JA",
21  "JS", "JNS", "JPE", "JNP",
22  #"L", "NL", "NG", "G"]
23  "JL", "JGE", "JLE", "JG",
24  "JCXZ", "JECXZ", "JRCXZ"]
25 
26 unconditional_branch = ['JMP', 'JMPF']
27 
28 f_isad = "AD"
29 f_s08 = "S08"
30 f_u08 = "U08"
31 f_s16 = "S16"
32 f_u16 = "U16"
33 f_s32 = "S32"
34 f_u32 = "U32"
35 f_s64 = "S64"
36 f_u64 = "U64"
37 f_imm = 'IMM'
38 
39 f_imm2size = {f_s08: 8, f_s16: 16, f_s32: 32, f_s64: 64,
40  f_u08: 8, f_u16: 16, f_u32: 32, f_u64: 64}
41 
42 
43 size2gpregs = {8: gpregs08, 16: gpregs16,
44  32: gpregs32, 64: gpregs64}
45 
46 
47 replace_regs64 = {
48  AL: RAX[:8], CL: RCX[:8], DL: RDX[:8], BL: RBX[:8],
49  AH: RAX[8:16], CH: RCX[8:16], DH: RDX[8:16], BH: RBX[8:16],
50  SPL: RSP[0:8], BPL: RBP[0:8], SIL: RSI[0:8], DIL: RDI[0:8],
51  R8B: R8[0:8], R9B: R9[0:8], R10B: R10[0:8], R11B: R11[0:8],
52  R12B: R12[0:8], R13B: R13[0:8], R14B: R14[0:8], R15B: R15[0:8],
53 
54  AX: RAX[:16], CX: RCX[:16], DX: RDX[:16], BX: RBX[:16],
55  SP: RSP[:16], BP: RBP[:16], SI: RSI[:16], DI: RDI[:16],
56  R8W: R8[:16], R9W: R9[:16], R10W: R10[:16], R11W: R11[:16],
57  R12W: R12[:16], R13W: R13[:16], R14W: R14[:16], R15W: R15[:16],
58 
59  EAX: RAX[:32], ECX: RCX[:32], EDX: RDX[:32], EBX: RBX[:32],
60  ESP: RSP[:32], EBP: RBP[:32], ESI: RSI[:32], EDI: RDI[:32],
61  R8D: R8[:32], R9D: R9[:32], R10D: R10[:32], R11D: R11[:32],
62  R12D: R12[:32], R13D: R13[:32], R14D: R14[:32], R15D: R15[:32],
63 
64  IP: RIP[:16], EIP: RIP[:32],
65 
66  ExprId("ST", 64): float_st0,
67  ExprId("ST(0)", 64): float_st0,
68  ExprId("ST(1)", 64): float_st1,
69  ExprId("ST(2)", 64): float_st2,
70  ExprId("ST(3)", 64): float_st3,
71  ExprId("ST(4)", 64): float_st4,
72  ExprId("ST(5)", 64): float_st5,
73  ExprId("ST(6)", 64): float_st6,
74  ExprId("ST(7)", 64): float_st7,
75 
76 }
77 
78 replace_regs32 = {
79  AL: EAX[:8], CL: ECX[:8], DL: EDX[:8], BL: EBX[:8],
80  AH: EAX[8:16], CH: ECX[8:16], DH: EDX[8:16], BH: EBX[8:16],
81 
82  AX: EAX[:16], CX: ECX[:16], DX: EDX[:16], BX: EBX[:16],
83  SP: ESP[:16], BP: EBP[:16], SI: ESI[:16], DI: EDI[:16],
84 
85  IP: EIP[:16],
86 
87 
88  ExprId("ST", 64): float_st0,
89  ExprId("ST(0)", 64): float_st0,
90  ExprId("ST(1)", 64): float_st1,
91  ExprId("ST(2)", 64): float_st2,
92  ExprId("ST(3)", 64): float_st3,
93  ExprId("ST(4)", 64): float_st4,
94  ExprId("ST(5)", 64): float_st5,
95  ExprId("ST(6)", 64): float_st6,
96  ExprId("ST(7)", 64): float_st7,
97 
98 }
99 
100 replace_regs16 = {
101  AL: AX[:8], CL: CX[:8], DL: DX[:8], BL: BX[:8],
102  AH: AX[8:16], CH: CX[8:16], DH: DX[8:16], BH: BX[8:16],
103 
104  AX: AX[:16], CX: CX[:16], DX: DX[:16], BX: BX[:16],
105  SP: SP[:16], BP: BP[:16], SI: SI[:16], DI: DI[:16],
106 
107 
108  ExprId("ST", 64): float_st0,
109  ExprId("ST(0)", 64): float_st0,
110  ExprId("ST(1)", 64): float_st1,
111  ExprId("ST(2)", 64): float_st2,
112  ExprId("ST(3)", 64): float_st3,
113  ExprId("ST(4)", 64): float_st4,
114  ExprId("ST(5)", 64): float_st5,
115  ExprId("ST(6)", 64): float_st6,
116  ExprId("ST(7)", 64): float_st7,
117 
118 }
119 
120 replace_regs = {16: replace_regs16,
121  32: replace_regs32,
122  64: replace_regs64}
123 
124 
125 # parser helper ###########
126 PLUS = Suppress("+")
127 MULT = Suppress("*")
128 
129 COLON = Suppress(":")
130 
131 
132 LBRACK = Suppress("[")
133 RBRACK = Suppress("]")
134 
135 dbreg = Group(gpregs16.parser | gpregs32.parser | gpregs64.parser)
136 gpreg = (gpregs08.parser | gpregs08_64.parser | gpregs16.parser |
137  gpregs32.parser | gpregs64.parser | gpregs_xmm.parser |
138  gpregs_mm.parser)
139 
140 
141 def reg2exprid(r):
142  if not r.name in all_regs_ids_byname:
143  raise ValueError('unknown reg')
144  return all_regs_ids_byname[r.name]
145 
146 
147 def parse_deref_reg(s, l, t):
148  t = t[0][0]
149  return t[0]
150 
151 
152 def parse_deref_int(s, l, t):
153  t = t[0]
154  return t[0]
155 
156 
157 def parse_deref_regint(s, l, t):
158  t = t[0]
159  r1 = reg2exprid(t[0][0])
160  i1 = ExprInt_from(r1, t[1].arg)
161  return r1 + i1
162 
163 
164 def parse_deref_regreg(s, l, t):
165  t = t[0]
166  return t[0][0] + t[1][0]
167 
168 
170  t = t[0]
171  r1 = reg2exprid(t[0][0])
172  r2 = reg2exprid(t[1][0])
173  i1 = ExprInt_from(r1, t[2].arg)
174  return r1 + r2 + i1
175 
176 
178  t = t[0]
179  r1 = reg2exprid(t[0][0])
180  r2 = reg2exprid(t[1][0])
181  i1 = ExprInt_from(r1, t[2].arg)
182  return r1 + (r2 * i1)
183 
184 
186  t = t[0]
187  r1 = reg2exprid(t[0][0])
188  r2 = reg2exprid(t[1][0])
189  i1 = ExprInt_from(r1, t[2].arg)
190  i2 = ExprInt_from(r1, t[3].arg)
191  return r1 + (r2 * i1) + i2
192 
193 
194 def parse_deref_intmreg(s, l, t):
195  t = t[0]
196  r1 = reg2exprid(t[0][0])
197  i1 = ExprInt_from(r1, t[1].arg)
198  return r1 * i1
199 
200 
202  t = t[0]
203  r1 = reg2exprid(t[0][0])
204  i1 = ExprInt_from(r1, t[1].arg)
205  i2 = ExprInt_from(r1, t[1].arg)
206  return (r1 * i1) + i2
207 
208 
209 def getreg(s, l, t):
210  t = t[0]
211  return t[0]
212 
213 
214 def parse_deref_ptr(s, l, t):
215  t = t[0]
216  return ExprMem(ExprOp('segm', t[0], t[1]))
217 
218 def parse_deref_segmoff(s, l, t):
219  t = t[0]
220  return ExprOp('segm', t[0], t[1])
221 
222 
223 variable, operand, base_expr = gen_base_expr()
224 
225 
226 def ast_id2expr(t):
227  if not t in mn_x86.regs.all_regs_ids_byname:
228  r = ExprId(asm_label(t))
229  else:
230  r = mn_x86.regs.all_regs_ids_byname[t]
231  return r
232 
233 
235  return ExprInt64(a)
236 
237 
238 my_var_parser = parse_ast(ast_id2expr, ast_int2expr)
239 base_expr.setParseAction(my_var_parser)
240 
241 int_or_expr = base_expr
242 
243 deref_mem_ad = Group(LBRACK + dbreg + RBRACK).setParseAction(parse_deref_reg)
244 deref_mem_ad |= Group(
245  LBRACK + int_or_expr + RBRACK).setParseAction(parse_deref_int)
246 deref_mem_ad |= Group(
247  LBRACK + dbreg + PLUS +
248  int_or_expr + RBRACK).setParseAction(parse_deref_regint)
249 deref_mem_ad |= Group(
250  LBRACK + dbreg + PLUS +
251  dbreg + RBRACK).setParseAction(parse_deref_regreg)
252 deref_mem_ad |= Group(
253  LBRACK + dbreg + PLUS + dbreg + PLUS +
254  int_or_expr + RBRACK).setParseAction(parse_deref_regregint)
255 deref_mem_ad |= Group(
256  LBRACK + dbreg + PLUS + dbreg + MULT +
257  int_or_expr + RBRACK).setParseAction(parse_deref_reg_intmreg)
258 deref_mem_ad |= Group(
259  LBRACK + dbreg + PLUS + dbreg + MULT + int_or_expr +
260  PLUS + int_or_expr + RBRACK).setParseAction(parse_deref_reg_intmreg_int)
261 deref_mem_ad |= Group(
262  LBRACK + dbreg + MULT +
263  int_or_expr + RBRACK).setParseAction(parse_deref_intmreg)
264 deref_mem_ad |= Group(
265  LBRACK + dbreg + MULT + int_or_expr +
266  PLUS + int_or_expr + RBRACK).setParseAction(parse_deref_intmregint)
267 
268 
269 deref_ptr = Group(int_or_expr + COLON +
270  int_or_expr).setParseAction(parse_deref_segmoff)
271 
272 
273 PTR = Suppress('PTR')
274 
275 
276 BYTE = Literal('BYTE')
277 WORD = Literal('WORD')
278 DWORD = Literal('DWORD')
279 QWORD = Literal('QWORD')
280 TBYTE = Literal('TBYTE')
281 XMMWORD = Literal('XMMWORD')
282 
283 MEMPREFIX2SIZE = {'BYTE': 8, 'WORD': 16, 'DWORD': 32,
284  'QWORD': 64, 'TBYTE': 80, 'XMMWORD': 128}
285 
286 SIZE2MEMPREFIX = dict((x[1], x[0]) for x in MEMPREFIX2SIZE.items())
287 
288 def parse_deref_mem(s, l, t):
289  t = t[0]
290  if len(t) == 2:
291  s, ptr = t
292  return ExprMem(ptr, MEMPREFIX2SIZE[s[0]])
293  elif len(t) == 3:
294  s, segm, ptr = t
295  return ExprMem(ExprOp('segm', segm[0], ptr), MEMPREFIX2SIZE[s[0]])
296  else:
297  raise ValueError('len(t) > 3')
298 
299 mem_size = Group(BYTE | DWORD | QWORD | WORD | TBYTE | XMMWORD)
300 deref_mem = Group(mem_size + PTR + Optional(Group(int_or_expr + COLON))
301  + deref_mem_ad).setParseAction(parse_deref_mem)
302 
303 
304 rmarg = Group(gpregs08.parser |
305  gpregs08_64.parser |
306  gpregs16.parser |
307  gpregs32.parser |
308  gpregs64.parser |
309  gpregs_mm.parser |
310  gpregs_xmm.parser
311  ).setParseAction(getreg)
312 
313 rmarg |= deref_mem
314 
315 
316 cl_or_imm = Group(r08_ecx.parser).setParseAction(getreg)
317 cl_or_imm |= int_or_expr
318 
319 
321  reg_info = r08_eax
322  parser = reg_info.parser
323 
324 
326  reg_info = r16_eax
327  parser = reg_info.parser
328 
329 
331  reg_info = r16_edx
332  parser = reg_info.parser
333 
334 
336  reg_info = r32_eax
337  parser = reg_info.parser
338 
339 
341  reg_info = r64_eax
342  parser = reg_info.parser
343 
344 
346  reg_info = r08_ecx
347  parser = reg_info.parser
348 
349 
350 invmode = {16: 32, 32: 16}
351 
352 
353 def opmode_prefix(mode):
354  size, opmode, admode = mode
355  if size in [16, 32]:
356  if opmode:
357  return invmode[size]
358  else:
359  return size
360  elif size == 64:
361  if opmode:
362  return 16
363  else:
364  return 32
365  raise NotImplementedError('not fully functional')
366 
367 
368 def admode_prefix(mode):
369  size, opmode, admode = mode
370  if size in [16, 32]:
371  if admode:
372  return invmode[size]
373  else:
374  return size
375  elif size == 64:
376  return 64
377  raise NotImplementedError('not fully functional')
378 
379 
380 def v_opmode_info(size, opmode, rex_w, stk):
381  if size in [16, 32]:
382  if opmode:
383  return invmode[size]
384  else:
385  return size
386  elif size == 64:
387  # Rex has the maximum priority
388  # Then opmode
389  # Then stacker
390  if rex_w == 1:
391  return 64
392  elif opmode == 1:
393  return 16
394  elif stk:
395  return 64
396  else:
397  return 32
398 
399 
400 def v_opmode(p):
401  stk = hasattr(p, 'stk')
402  return v_opmode_info(p.mode, p.opmode, p.rex_w.value, stk)
403 
404 
405 def v_admode_info(size, admode):
406  if size in [16, 32]:
407  if admode:
408  return invmode[size]
409  else:
410  return size
411  elif size == 64:
412  if admode == 1:
413  return 32
414  return 64
415 
416 
417 def v_admode(p):
418  return v_admode_info(p.mode, p.admode)
419 
420 
421 def offsize(p):
422  if p.opmode:
423  return 16
424  else:
425  return p.mode
426 
427 
428 def get_prefix(s):
429  g = re.search('(\S+)(\s+)', s)
430  if not g:
431  return None, s
432  prefix, b = g.groups()
433  return prefix, s[len(prefix) + len(b):]
434 
435 
436 repeat_mn = ["INS", "OUTS",
437  "MOVSB", "MOVSW", "MOVSD", "MOVSQ",
438  "SCASB", "SCASW", "SCASD", "SCASQ",
439  "LODSB", "LODSW", "LODSD", "LODSQ",
440  "STOSB", "STOSW", "STOSD", "STOSQ",
441  "CMPSB", "CMPSW", "CMPSD", "CMPSQ",
442  ]
443 
444 segm2enc = {CS: 1, SS: 2, DS: 3, ES: 4, FS: 5, GS: 6}
445 enc2segm = dict([(x[1], x[0]) for x in segm2enc.items()])
446 
447 
448 class group:
449 
450  def __init__(self):
451  self.value = None
452 
453 
455 
456  def __init__(self):
457  self.except_on_instr = False
458  self.g1 = group()
459  self.g2 = group()
460  self.vopmode = None
461  self.stk = False
462  self.v_opmode = None
463  self.v_admode = None
464  self.prefixed = ''
465 
466 
468  delayslot = 0
469 
470  def __init__(self, *args, **kargs):
471  super(instruction_x86, self).__init__(*args, **kargs)
472 
473  def v_opmode(self):
474  return self.additional_info.v_opmode
475 
476  def v_admode(self):
477  return self.additional_info.v_admode
478 
479  def dstflow(self):
480  if self.name in conditional_branch + unconditional_branch:
481  return True
482  if self.name.startswith('LOOP'):
483  return True
484  return self.name in ['CALL']
485 
486  def dstflow2label(self, symbol_pool):
487  if self.additional_info.g1.value & 6 and self.name in repeat_mn:
488  return
489  expr = self.args[0]
490  if isinstance(expr, ExprId):
491  if not isinstance(expr.name, asm_label) and expr not in all_regs_ids:
492  raise ValueError("ExprId must be a label or a register")
493  elif isinstance(expr, ExprInt):
494  ad = expr.arg + int(self.offset)
495  l = symbol_pool.getby_offset_create(ad)
496  s = ExprId(l, expr.size)
497  self.args[0] = s
498  else:
499  return
500 
501  def breakflow(self):
502  if self.name in conditional_branch + unconditional_branch:
503  return True
504  if self.name.startswith('LOOP'):
505  return True
506  if self.name.startswith('RET'):
507  return True
508  if self.name.startswith('INT'):
509  return True
510  if self.name.startswith('SYS'):
511  return True
512  return self.name in ['CALL', 'HLT', 'IRET', 'IRETD', 'IRETQ', 'ICEBP']
513 
514  def splitflow(self):
515  if self.name in conditional_branch:
516  return True
517  if self.name in unconditional_branch:
518  return False
519  if self.name.startswith('LOOP'):
520  return True
521  if self.name.startswith('INT'):
522  return True
523  if self.name.startswith('SYS'):
524  return True
525  return self.name in ['CALL']
526 
527  def setdstflow(self, a):
528  return
529 
530  def is_subcall(self):
531  return self.name in ['CALL']
532 
533  def getdstflow(self, symbol_pool):
534  if self.additional_info.g1.value & 6 and self.name in repeat_mn:
535  ad = int(self.offset)
536  l = symbol_pool.getby_offset_create(ad)
537  s = ExprId(l, self.v_opmode())
538  return [s]
539  return [self.args[0]]
540 
541  def get_symbol_size(self, symbol, symbol_pool):
542  return self.mode
543 
544  def fixDstOffset(self):
545  expr = self.args[0]
546  if self.offset is None:
547  raise ValueError('symbol not resolved %s' % l)
548  if not isinstance(expr, ExprInt):
549  log.warning('dynamic dst %r', expr)
550  return
551  self.args[0] = ExprInt(int(expr.arg) - self.offset, self.mode)
552 
553  def get_info(self, c):
554  self.additional_info.g1.value = c.g1.value
555  self.additional_info.g2.value = c.g2.value
556  self.additional_info.stk = hasattr(c, 'stk')
557  self.additional_info.v_opmode = c.v_opmode()
558  self.additional_info.v_admode = c.v_admode()
559  self.additional_info.prefix = c.prefix
560  self.additional_info.prefixed = getattr(c, "prefixed", "")
561 
562  def __str__(self):
563  o = super(instruction_x86, self).__str__()
564  if self.additional_info.g1.value & 1:
565  o = "LOCK %s" % o
566  if self.additional_info.g1.value & 2:
567  if getattr(self.additional_info.prefixed, 'default', "") != "\xF2":
568  o = "REPNE %s" % o
569  if self.additional_info.g1.value & 4:
570  if getattr(self.additional_info.prefixed, 'default', "") != "\xF3":
571  o = "REPE %s" % o
572  return o
573 
574  def get_args_expr(self):
575  args = []
576  for a in self.args:
577  a = a.replace_expr(replace_regs[self.mode])
578  args.append(a)
579  return args
580 
581  @staticmethod
582  def arg2str(expr, pos=None):
583  if isinstance(expr, ExprId) or isinstance(expr, ExprInt):
584  o = str(expr)
585  elif isinstance(expr, ExprMem):
586  sz = SIZE2MEMPREFIX[expr.size]
587  segm = ""
588  if expr.is_op_segm():
589  segm = "%s:" % expr.arg.args[0]
590  expr = expr.arg.args[1]
591  else:
592  expr = expr.arg
593  if isinstance(expr, ExprOp):
594  s = str(expr).replace('(', '').replace(')', '')
595  else:
596  s = str(expr)
597  o = sz + ' PTR %s[%s]' % (segm, s)
598  elif isinstance(expr, ExprOp) and expr.op == 'segm':
599  o = "%s:%s" % (expr.args[0], expr.args[1])
600  else:
601  raise ValueError('check this %r' % expr)
602  return "%s" % o
603 
604 
605 
606 class mn_x86(cls_mn):
607  name = "x86"
608  prefix_op_size = False
609  prefix_ad_size = False
610  regs = regs_module
611  all_mn = []
612  all_mn_mode = defaultdict(list)
613  all_mn_name = defaultdict(list)
614  all_mn_inst = defaultdict(list)
615  bintree = {}
616  num = 0
617  delayslot = 0
618  pc = {16: IP, 32: EIP, 64: RIP}
619  sp = {16: SP, 32: ESP, 64: RSP}
620  instruction = instruction_x86
621  max_instruction_len = 15
622 
623  @classmethod
624  def getpc(cls, attrib):
625  return cls.pc[attrib]
626 
627  @classmethod
628  def getsp(cls, attrib):
629  return cls.sp[attrib]
630 
631  def v_opmode(self):
632  if hasattr(self, 'stk'):
633  stk = 1
634  else:
635  stk = 0
636  return v_opmode_info(self.mode, self.opmode, self.rex_w.value, stk)
637 
638  def v_admode(self):
639  size, opmode, admode = self.mode, self.opmode, self.admode
640  if size in [16, 32]:
641  if admode:
642  return invmode[size]
643  else:
644  return size
645  elif size == 64:
646  if admode == 1:
647  return 32
648  return 64
649 
650  def additional_info(self):
651  info = additional_info()
652  info.g1.value = self.g1.value
653  info.g2.value = self.g2.value
654  info.stk = hasattr(self, 'stk')
655  info.v_opmode = self.v_opmode()
656  info.prefixed = ""
657  if hasattr(self, 'prefixed'):
658  info.prefixed = self.prefixed.default
659  return info
660 
661  @classmethod
662  def check_mnemo(cls, fields):
663  pass
664 
665  @classmethod
666  def getmn(cls, name):
667  return name.upper()
668 
669  @classmethod
670  def mod_fields(cls, fields):
671  prefix = [d_g1, d_g2, d_rex_p, d_rex_w, d_rex_r, d_rex_x, d_rex_b]
672  return prefix + fields
673 
674  @classmethod
675  def gen_modes(cls, subcls, name, bases, dct, fields):
676  dct['mode'] = None
677  return [(subcls, name, bases, dct, fields)]
678 
679  @classmethod
680  def fromstring(cls, s, mode):
681  pref = 0
682  prefix, new_s = get_prefix(s)
683  if prefix == "LOCK":
684  pref |= 1
685  s = new_s
686  elif prefix == "REPNE":
687  pref |= 2
688  s = new_s
689  elif prefix == "REPE":
690  pref |= 4
691  s = new_s
692  c = super(mn_x86, cls).fromstring(s, mode)
693  c.additional_info.g1.value = pref
694  return c
695 
696  @classmethod
697  def pre_dis(cls, v, mode, offset):
698  offset_o = offset
699  pre_dis_info = {'opmode': 0,
700  'admode': 0,
701  'g1': 0,
702  'g2': 0,
703  'rex_p': 0,
704  'rex_w': 0,
705  'rex_r': 0,
706  'rex_x': 0,
707  'rex_b': 0,
708  'prefix': "",
709  'prefixed': "",
710  }
711  while True:
712  c = v.getbytes(offset)
713  if c == '\x66':
714  pre_dis_info['opmode'] = 1
715  elif c == '\x67':
716  pre_dis_info['admode'] = 1
717  elif c == '\xf0':
718  pre_dis_info['g1'] = 1
719  elif c == '\xf2':
720  pre_dis_info['g1'] = 2
721  elif c == '\xf3':
722  pre_dis_info['g1'] = 4
723 
724  elif c == '\x2e':
725  pre_dis_info['g2'] = 1
726  elif c == '\x36':
727  pre_dis_info['g2'] = 2
728  elif c == '\x3e':
729  pre_dis_info['g2'] = 3
730  elif c == '\x26':
731  pre_dis_info['g2'] = 4
732  elif c == '\x64':
733  pre_dis_info['g2'] = 5
734  elif c == '\x65':
735  pre_dis_info['g2'] = 6
736 
737  elif mode == 64 and c in '@ABCDEFGHIJKLMNO':
738  x = ord(c)
739  pre_dis_info['rex_p'] = 1
740  pre_dis_info['rex_w'] = (x >> 3) & 1
741  pre_dis_info['rex_r'] = (x >> 2) & 1
742  pre_dis_info['rex_x'] = (x >> 1) & 1
743  pre_dis_info['rex_b'] = (x >> 0) & 1
744  offset += 1
745  break
746  else:
747  c = ''
748  break
749  pre_dis_info['prefix'] += c
750  offset += 1
751  return pre_dis_info, v, mode, offset, offset - offset_o
752 
753  @classmethod
754  def get_cls_instance(cls, cc, mode, infos=None):
755  for opmode in [0, 1]:
756  for admode in [0, 1]:
757  c = cc()
758  c.init_class()
759 
760  c.reset_class()
761  c.add_pre_dis_info()
762  c.dup_info(infos)
763  c.mode = mode
764  c.opmode = opmode
765  c.admode = admode
766 
767  if not hasattr(c, 'stk') and hasattr(c, "fopmode") and c.fopmode.mode == 64:
768  c.rex_w.value = 1
769  yield c
770 
771  def post_dis(self):
772  if self.g2.value:
773  for a in self.args:
774  if not isinstance(a.expr, ExprMem):
775  continue
776  m = a.expr
777  a.expr = ExprMem(
778  ExprOp('segm', enc2segm[self.g2.value], m.arg), m.size)
779  if self.name in ['LEA', 'LDS', 'LES', 'LFS', 'LGS', 'LSS']:
780  if not isinstance(self.args[1].expr, ExprMem):
781  return None
782  return self
783 
784  def dup_info(self, infos):
785  if infos is not None:
786  self.g1.value = infos.g1.value
787  self.g2.value = infos.g2.value
788 
789  def reset_class(self):
790  super(mn_x86, self).reset_class()
791  if hasattr(self, "opmode"):
792  del(self.opmode)
793  if hasattr(self, "admode"):
794  del(self.admode)
795 
796  def add_pre_dis_info(self, pre_dis_info=None):
797  if pre_dis_info is None:
798  return True
799  if hasattr(self, "prefixed") and self.prefixed.default == "\x66":
800  pre_dis_info['opmode'] = 0
801  self.opmode = pre_dis_info['opmode']
802  self.admode = pre_dis_info['admode']
803 
804  if hasattr(self, 'no_xmm_pref') and\
805  pre_dis_info['prefix'] and\
806  pre_dis_info['prefix'][-1] in '\x66\xf2\xf3':
807  return False
808  if (hasattr(self, "prefixed") and
809  not pre_dis_info['prefix'].endswith(self.prefixed.default)):
810  return False
811  if (self.rex_w.value is not None and
812  self.rex_w.value != pre_dis_info['rex_w']):
813  return False
814  else:
815  self.rex_w.value = pre_dis_info['rex_w']
816  self.rex_r.value = pre_dis_info['rex_r']
817  self.rex_b.value = pre_dis_info['rex_b']
818  self.rex_x.value = pre_dis_info['rex_x']
819  self.rex_p.value = pre_dis_info['rex_p']
820  self.g1.value = pre_dis_info['g1']
821  self.g2.value = pre_dis_info['g2']
822  self.prefix = pre_dis_info['prefix']
823  return True
824 
825  def post_asm(self, v):
826  return v
827 
828 
829  def gen_prefix(self):
830  v = ""
831  rex = 0x40
832  if self.g1.value is None:
833  self.g1.value = 0
834  if self.g2.value is None:
835  self.g2.value = 0
836 
837  if self.rex_w.value:
838  rex |= 0x8
839  if self.rex_r.value:
840  rex |= 0x4
841  if self.rex_x.value:
842  rex |= 0x2
843  if self.rex_b.value:
844  rex |= 0x1
845  if rex != 0x40 or self.rex_p.value == 1:
846  v = chr(rex) + v
847 
848  if hasattr(self, 'prefixed'):
849  v = self.prefixed.default + v
850 
851  if self.g1.value & 1:
852  v = "\xf0" + v
853  if self.g1.value & 2:
854  if hasattr(self, 'no_xmm_pref'):
855  return None
856  v = "\xf2" + v
857  if self.g1.value & 4:
858  if hasattr(self, 'no_xmm_pref'):
859  return None
860  v = "\xf3" + v
861  if self.g2.value:
862  v = {1: '\x2e', 2: '\x36', 3: '\x3e', 4:
863  '\x26', 5: '\x64', 6: '\x65'}[self.g2.value] + v
864  # mode prefix
865  if hasattr(self, "admode") and self.admode:
866  v = "\x67" + v
867 
868  if hasattr(self, "opmode") and self.opmode:
869  if hasattr(self, 'no_xmm_pref'):
870  return None
871  v = "\x66" + v
872  return v
873 
874  def encodefields(self, decoded):
875  v = super(mn_x86, self).encodefields(decoded)
876  prefix = self.gen_prefix()
877  if prefix is None:
878  return None
879  return prefix + v
880 
881  def getnextflow(self, symbol_pool):
882  raise NotImplementedError('not fully functional')
883 
885  return [ExprAff(mRIP[self.mode],
886  ExprInt_from(mRIP[self.mode], self.offset + self.l))]
887 
888  @classmethod
889  def filter_asm_candidates(cls, instr, candidates):
890 
891  cand_same_mode = []
892  cand_diff_mode = []
893  out = []
894  for c, v in candidates:
895  if (hasattr(c, 'no_xmm_pref') and
896  (c.g1.value & 2 or c.g1.value & 4 or c.opmode)):
897  continue
898  if hasattr(c, "fopmode") and v_opmode(c) != c.fopmode.mode:
899  continue
900  if hasattr(c, "fadmode") and v_admode(c) != c.fadmode.mode:
901  continue
902  # relative dstflow must not have opmode set
903  # (affect IP instead of EIP for instance)
904  if (instr.dstflow() and
905  instr.name not in ["JCXZ", "JECXZ", "JRCXZ"] and
906  len(instr.args) == 1 and
907  isinstance(instr.args[0], ExprInt) and c.opmode):
908  continue
909 
910  out.append((c, v))
911  candidates = out
912  for c, v in candidates:
913  if v_opmode(c) == instr.mode:
914  cand_same_mode += v
915  for c, v in candidates:
916  if v_opmode(c) != instr.mode:
917  cand_diff_mode += v
918  cand_same_mode.sort(key=len)
919  cand_diff_mode.sort(key=len)
920  return cand_same_mode + cand_diff_mode
921 
922 
924  prio = 1
925 
926  def divert(self, i, candidates):
927  out = []
928  for candidate in candidates:
929  cls, name, bases, dct, fields = candidate
930  fopmode = opmode_prefix(
931  (dct['mode'], dct['opmode'], dct['admode']))
932  mode = dct['mode']
933  size, opmode, admode = dct['mode'], dct['opmode'], dct['admode']
934  # no mode64 existance in name means no 64bit version of mnemo
935  if mode == 64:
936  if mode in self.args['name']:
937  nfields = fields[:]
938  f, i = getfieldindexby_name(nfields, 'rex_w')
939  f = bs("1", l=0, cls=(bs_fbit,), fname="rex_w")
940  osize = v_opmode_info(size, opmode, 1, 0)
941  nfields[i] = f
942  nfields = nfields[:-1]
943  args = dict(self.args)
944  ndct = dict(dct)
945  if osize in self.args['name']:
946  ndct['name'] = self.args['name'][osize]
947  out.append((cls, ndct['name'], bases, ndct, nfields))
948 
949  nfields = fields[:]
950  nfields = nfields[:-1]
951  f, i = getfieldindexby_name(nfields, 'rex_w')
952  f = bs("0", l=0, cls=(bs_fbit,), fname="rex_w")
953  osize = v_opmode_info(size, opmode, 0, 0)
954  nfields[i] = f
955  args = dict(self.args)
956  ndct = dict(dct)
957  if osize in self.args['name']:
958  ndct['name'] = self.args['name'][osize]
959  out.append((cls, ndct['name'], bases, ndct, nfields))
960  else:
961  l = opmode_prefix((dct['mode'], dct['opmode'], dct['admode']))
962  osize = v_opmode_info(size, opmode, None, 0)
963  nfields = fields[:-1]
964  args = dict(self.args)
965  ndct = dict(dct)
966  if osize in self.args['name']:
967  ndct['name'] = self.args['name'][osize]
968  out.append((cls, ndct['name'], bases, ndct, nfields))
969  return out
970 
971 
973  prio = 1
974 
975  def divert(self, i, candidates):
976  out = []
977  for candidate in candidates:
978  cls, name, bases, dct, fields = candidate
979  fopmode = opmode_prefix(
980  (dct['mode'], dct['opmode'], dct['admode']))
981  mode = dct['mode']
982  size, opmode, admode = dct['mode'], dct['opmode'], dct['admode']
983 
984  nfields = fields[:]
985  nfields = nfields[:-1]
986  args = dict(self.args)
987  ndct = dict(dct)
988  if mode == 64:
989  if admode:
990  ndct['name'] = "JECXZ"
991  else:
992  ndct['name'] = "JRCXZ"
993  elif mode == 32:
994  if admode:
995  ndct['name'] = "JCXZ"
996  else:
997  ndct['name'] = "JECXZ"
998  elif mode == 16:
999  if admode:
1000  ndct['name'] = "JECXZ"
1001  else:
1002  ndct['name'] = "JCXZ"
1003  else:
1004  raise ValueError('unhandled mode')
1005  out.append((cls, ndct['name'], bases, ndct, nfields))
1006  return out
1007 
1008 
1010  prio = 1
1011 
1012  def divert(self, i, candidates):
1013  out = []
1014  for candidate in candidates:
1015  cls, name, bases, dct, fields = candidate
1016  fopmode = opmode_prefix(
1017  (dct['mode'], dct['opmode'], dct['admode']))
1018  size, opmode, admode = dct['mode'], dct['opmode'], dct['admode']
1019 
1020  mode = dct['mode']
1021  l = opmode_prefix((dct['mode'], dct['opmode'], dct['admode']))
1022  osize = v_opmode_info(size, opmode, None, 0)
1023  nfields = fields[:-1]
1024  args = dict(self.args)
1025  ndct = dict(dct)
1026  if mode == 64 or osize == 32:
1027  ndct['name'] = self.args['name'][mode]
1028  else:
1029  ndct['name'] = self.args['name'][16]
1030  out.append((cls, ndct['name'], bases, ndct, nfields))
1031  return out
1032 
1033 
1035  parser = base_expr
1036 
1037  def decodeval(self, v):
1038  return swap_uint(self.l, v)
1039 
1040  def encodeval(self, v):
1041  return swap_uint(self.l, v)
1042 
1043 
1045  parser = base_expr
1046 
1047  def decodeval(self, v):
1048  return self.ival
1049 
1050  def encodeval(self, v):
1051  if v != self.ival:
1052  return False
1053  return self.ival
1054 
1055 
1057  intsize = 8
1058  intmask = (1 << intsize) - 1
1059 
1060 
1062  intsize = 16
1063  intmask = (1 << intsize) - 1
1064 
1065 
1067  intsize = 32
1068  intmask = (1 << intsize) - 1
1069 
1070 
1072  intsize = 64
1073  intmask = (1 << intsize) - 1
1074 
1075 
1077  intsize = 8
1078  intmask = (1 << intsize) - 1
1079 
1080  def encode(self):
1081  return True
1082 
1083  def decode(self, v):
1084  v = swap_uint(self.l, v)
1085  p = self.parent
1086  admode = p.v_admode()
1087  value = sign_ext(v, self.intsize, admode)
1088  self.expr = ExprInt(value, admode)
1089  return True
1090 
1091 
1093  intsize = 16
1094  intmask = (1 << intsize) - 1
1095 
1096 
1098  intsize = 32
1099  intmask = (1 << intsize) - 1
1100 
1101 
1103  intsize = 64
1104  intmask = (1 << intsize) - 1
1105 
1106 
1108  in_size = 8
1109  out_size = 16
1110 
1111  def myexpr(self, x):
1112  return ExprInt16(x)
1113 
1114  def int2expr(self, v):
1115  return self.myexpr(v)
1116 
1117  def expr2int(self, e):
1118  if not isinstance(e, ExprInt):
1119  return None
1120  v = int(e.arg)
1121  if v & ~((1 << self.l) - 1) != 0:
1122  return None
1123  return v
1124 
1125  def decode(self, v):
1126  v = v & self.lmask
1127  v = self.decodeval(v)
1128  if self.parent.v_opmode() == 64:
1129  self.expr = ExprInt64(sign_ext(v, self.in_size, 64))
1130  else:
1131  if (1 << (self.l - 1)) & v:
1132  v = sign_ext(v, self.l, self.out_size)
1133  self.expr = self.myexpr(v)
1134  return True
1135 
1136  def encode(self):
1137  if not isinstance(self.expr, ExprInt):
1138  return False
1139  v = int(self.expr.arg)
1140  opmode = self.parent.v_opmode()
1141 
1142  out_size = self.out_size
1143  if opmode != self.out_size:
1144  if opmode == 32 and self.out_size == 64:
1145  out_size = opmode
1146  if v == sign_ext(
1147  int(v & ((1 << self.in_size) - 1)), self.in_size, out_size):
1148  pass
1149  else:
1150  # test with rex_w
1151  self.parent.rex_w.value = 1
1152  opmode = self.parent.v_opmode()
1153  out_size = opmode
1154  if (v != sign_ext(
1155  int(v & ((1 << self.in_size) - 1)),
1156  self.in_size, out_size)):
1157  return False
1158  if v != sign_ext(
1159  int(v & ((1 << self.in_size) - 1)), self.in_size, out_size):
1160  return False
1161  v = self.encodeval(v)
1162  self.value = (v & 0xffffffff) & self.lmask
1163  return True
1164 
1165  def decodeval(self, v):
1166  return swap_uint(self.l, v)
1167 
1168  def encodeval(self, v):
1169  return swap_sint(self.l, v)
1170 
1171 
1173  in_size = 8
1174  out_size = 32
1175 
1176  def myexpr(self, x):
1177  return ExprInt32(x)
1178 
1179  def decode(self, v):
1180  v = v & self.lmask
1181  v = self.decodeval(v)
1182  if self.parent.rex_w.value == 1:
1183  v = ExprInt64(sign_ext(v, self.in_size, 64))
1184  else:
1185  v = ExprInt32(sign_ext(v, self.in_size, 32))
1186 
1187  self.expr = v
1188  return True
1189 
1190 
1192  in_size = 8
1193  out_size = 64
1194 
1195  def myexpr(self, x):
1196  return ExprInt64(x)
1197 
1198 
1200  in_size = 32
1201  out_size = 64
1202 
1203  def myexpr(self, x):
1204  return ExprInt64(x)
1205 
1206 
1207 class bs_eax(m_arg):
1208  reg_info = r_eax_all
1209  rindex = 0
1210  parser = reg_info.parser
1211 
1212  def decode(self, v):
1213  p = self.parent
1214  expr = None
1215  if hasattr(p, 'w8') and p.w8.value == 0:
1216  expr = regs08_expr[self.rindex]
1217  else:
1218  expr = size2gpregs[p.v_opmode()].expr[self.rindex]
1219  self.expr = expr
1220  return True
1221 
1222  def encode(self):
1223  self.value = 0
1224  p = self.parent
1225  expr = self.expr
1226  osize = p.v_opmode()
1227  if hasattr(p, 'w8'):
1228  if p.w8.value is None:
1229  # XXX TODO: priority in w8 erase?
1230  if expr.size == 8:
1231  p.w8.value = 0
1232  else:
1233  p.w8.value = 1
1234  if hasattr(p, 'w8') and p.w8.value == 0:
1235  return expr == regs08_expr[self.rindex]
1236  elif p.mode in [16, 32]:
1237  return expr == size2gpregs[osize].expr[self.rindex]
1238  elif p.mode == 64:
1239  if expr == size2gpregs[64].expr[self.rindex]:
1240  p.rex_w.value = 1
1241  return True
1242  elif expr == size2gpregs[osize].expr[self.rindex]:
1243  return True
1244  return False
1245  return False
1246 
1247 class bs_seg(m_arg):
1248  reg_info = r_eax_all
1249  rindex = 0
1250  parser = reg_info.parser
1251 
1252  def decode(self, v):
1253  self.expr = self.reg_info.expr[0]
1254  return True
1255 
1256  def encode(self):
1257  self.value = 0
1258  return self.expr == self.reg_info.expr[0]
1259 
1260 
1262  reg_info = r_edx_all
1263  rindex = 2
1264  parser = reg_info.parser
1265 
1266 
1267 class bs_st(bs_eax):
1268  reg_info = r_st_all
1269  rindex = 0
1270  parser = reg_info.parser
1271 
1272 
1273 class bs_cs(bs_seg):
1274  reg_info = r_cs_all
1275  rindex = 0
1276  parser = reg_info.parser
1277 
1278 
1279 class bs_ds(bs_seg):
1280  reg_info = r_ds_all
1281  rindex = 0
1282  parser = reg_info.parser
1283 
1284 
1285 class bs_es(bs_seg):
1286  reg_info = r_es_all
1287  rindex = 0
1288  parser = reg_info.parser
1289 
1290 
1291 class bs_ss(bs_seg):
1292  reg_info = r_ss_all
1293  rindex = 0
1294  parser = reg_info.parser
1295 
1296 
1297 class bs_fs(bs_seg):
1298  reg_info = r_fs_all
1299  rindex = 0
1300  parser = reg_info.parser
1301 
1302 
1303 class bs_gs(bs_seg):
1304  reg_info = r_gs_all
1305  rindex = 0
1306  parser = reg_info.parser
1307 
1308 
1310  reg_info = r_st_all
1311  parser = reg_info.parser
1312 
1313 
1315  bsname = "sib_scale"
1316 
1317  def divert(self, i, candidates):
1318  out = []
1319  done = False
1320  for cls, name, bases, dct, fields in candidates:
1321  if (not (admode_prefix(
1322  (dct['mode'], dct['opmode'], dct['admode'])) != 16 and
1323  'rm' in dct and dct['rm'] == 0b100 and
1324  'mod' in dct and dct['mod'] != 0b11)):
1325  ndct = dict(dct)
1326  nfields = fields[:]
1327  nfields[i] = None
1328  ndct[self.args['fname']] = None
1329  out.append((cls, ndct['name'], bases, ndct, nfields))
1330  continue
1331 
1332  nfields = fields[:]
1333  args = dict(self.args)
1334  ndct = dict(dct)
1335  f = bs(**args)
1336  nfields[i] = f
1337  ndct[self.args['fname']] = None
1338  out.append((cls, ndct['name'], bases, ndct, nfields))
1339  return out
1340 
1341 
1343  pass
1344 
1345 
1346 class bs_sib_base(bs_sib_scale):
1347  pass
1348 
1349 
1351 
1352  def divert(self, i, candidates):
1353  out = []
1354  done = False
1355  for cls, name, bases, dct, fields in candidates:
1356  ndct = dict(dct)
1357  nfields = fields[:]
1358  if (admode_prefix(
1359  (dct['mode'], dct['opmode'], dct['admode'])) == 16):
1360  if 'mod' in dct and dct['mod'] == 0b00 and \
1361  'rm' in dct and dct['rm'] == 0b110:
1362  nfields[i] = bs(
1363  l=16, cls=(x86_16_ne,), fname=self.args['fname'])
1364  ndct[self.args['fname']] = True
1365  out.append((cls, ndct['name'], bases, ndct, nfields))
1366  continue
1367  elif 'mod' in dct and dct['mod'] == 0b01:
1368  nfields[i] = bs(
1369  l=8, cls=(x86_08_ne,), fname=self.args['fname'])
1370  ndct[self.args['fname']] = True
1371  out.append((cls, ndct['name'], bases, ndct, nfields))
1372  continue
1373  elif 'mod' in dct and dct['mod'] == 0b10:
1374  nfields[i] = bs(
1375  l=16, cls=(x86_16_ne,), fname=self.args['fname'])
1376  ndct[self.args['fname']] = True
1377  out.append((cls, ndct['name'], bases, ndct, nfields))
1378  continue
1379  else:
1380  if 'mod' in dct and dct['mod'] == 0b00 and \
1381  'rm' in dct and dct['rm'] == 0b101:
1382  nfields[i] = bs(
1383  l=32, cls=(x86_32_ne,), fname=self.args['fname'])
1384  ndct[self.args['fname']] = True
1385  out.append((cls, ndct['name'], bases, ndct, nfields))
1386  continue
1387  elif 'mod' in dct and dct['mod'] == 0b01:
1388  nfields[i] = bs(
1389  l=8, cls=(x86_08_ne,), fname=self.args['fname'])
1390  ndct[self.args['fname']] = True
1391  out.append((cls, ndct['name'], bases, ndct, nfields))
1392  continue
1393  elif 'mod' in dct and dct['mod'] == 0b10:
1394  nfields[i] = bs(
1395  l=32, cls=(x86_32_ne,), fname=self.args['fname'])
1396  ndct[self.args['fname']] = True
1397  out.append((cls, ndct['name'], bases, ndct, nfields))
1398  continue
1399 
1400  nfields[i] = None
1401  ndct[self.args['fname']] = None
1402  out.append((cls, ndct['name'], bases, ndct, nfields))
1403  return out
1404 
1405 
1406 def getmodrm(c):
1407  return (c >> 6) & 3, (c >> 3) & 7, c & 7
1408 
1409 
1410 def setmodrm(mod, re, rm):
1411  return ((mod & 3) << 6) | ((re & 7) << 3) | (rm & 7)
1412 
1413 
1414 def sib(c):
1415  return modrm(c)
1416 
1417 db_afs_64 = []
1418 sib_64_s08_ebp = []
1419 
1420 
1422  global db_afs_64, sib_64_s08_ebp
1423  ebp = 5
1424 
1425  sib_s08_ebp = [{f_isad: True} for i in range(0x100)]
1426  sib_u32_ebp = [{f_isad: True} for i in range(0x100)]
1427  sib_u32 = [{f_isad: True} for i in range(0x100)]
1428 
1429  sib_u64 = []
1430  for rex_x in xrange(2):
1431  o = []
1432  for rex_b in xrange(2):
1433  x = [{f_isad: True} for i in range(0x100)]
1434  o.append(x)
1435  sib_u64.append(o)
1436 
1437  sib_u64_ebp = []
1438  for rex_x in xrange(2):
1439  o = []
1440  for rex_b in xrange(2):
1441  x = [{f_isad: True} for i in range(0x100)]
1442  o.append(x)
1443  sib_u64_ebp.append(o)
1444 
1445  sib_64_s08_ebp = []
1446  for rex_x in xrange(2):
1447  o = []
1448  for rex_b in xrange(2):
1449  x = [{f_isad: True} for i in range(0x100)]
1450  o.append(x)
1451  sib_64_s08_ebp.append(o)
1452 
1453  for sib_rez in [sib_s08_ebp,
1454  sib_u32_ebp,
1455  sib_u32,
1456  sib_64_s08_ebp,
1457  sib_u64_ebp,
1458  sib_u64,
1459  ]:
1460  for index in range(0x100):
1461  ss, i, b = getmodrm(index)
1462 
1463  if b == 0b101:
1464  if sib_rez == sib_s08_ebp:
1465  sib_rez[index][f_imm] = f_s08
1466  sib_rez[index][ebp] = 1
1467  elif sib_rez == sib_u32_ebp:
1468  sib_rez[index][f_imm] = f_u32
1469  sib_rez[index][ebp] = 1
1470  elif sib_rez == sib_u32:
1471  sib_rez[index][f_imm] = f_u32
1472  elif sib_rez == sib_u64_ebp:
1473  for rex_b in xrange(2):
1474  for rex_x in xrange(2):
1475  sib_rez[rex_x][rex_b][index][f_imm] = f_u32
1476  sib_rez[rex_x][rex_b][index][ebp + 8 * rex_b] = 1
1477  elif sib_rez == sib_u64:
1478  for rex_b in xrange(2):
1479  for rex_x in xrange(2):
1480  sib_rez[rex_x][rex_b][index][f_imm] = f_u32
1481  elif sib_rez == sib_64_s08_ebp:
1482  for rex_b in xrange(2):
1483  for rex_x in xrange(2):
1484  sib_rez[rex_x][rex_b][index][f_imm] = f_s08
1485  sib_rez[rex_x][rex_b][index][ebp + 8 * rex_b] = 1
1486 
1487  else:
1488  if sib_rez == sib_s08_ebp:
1489  sib_rez[index][b] = 1
1490  sib_rez[index][f_imm] = f_s08
1491  elif sib_rez == sib_u32_ebp:
1492  sib_rez[index][b] = 1
1493  sib_rez[index][f_imm] = f_u32
1494  elif sib_rez == sib_u32:
1495  sib_rez[index][b] = 1
1496  elif sib_rez == sib_u64_ebp:
1497  for rex_b in xrange(2):
1498  for rex_x in xrange(2):
1499  sib_rez[rex_x][rex_b][index][b + 8 * rex_b] = 1
1500  sib_rez[rex_x][rex_b][index][f_imm] = f_u32
1501  elif sib_rez == sib_u64:
1502  for rex_b in xrange(2):
1503  for rex_x in xrange(2):
1504  sib_rez[rex_x][rex_b][index][b + 8 * rex_b] = 1
1505  elif sib_rez == sib_64_s08_ebp:
1506  for rex_b in xrange(2):
1507  for rex_x in xrange(2):
1508  sib_rez[rex_x][rex_b][index][f_imm] = f_s08
1509  sib_rez[rex_x][rex_b][index][b + 8 * rex_b] = 1
1510 
1511  if i == 0b100 and sib_rez in [sib_s08_ebp, sib_u32_ebp, sib_u32]:
1512  continue
1513 
1514  if sib_rez in [sib_s08_ebp, sib_u32_ebp, sib_u32]:
1515  tmp = i
1516  if not tmp in sib_rez[index]:
1517  sib_rez[index][tmp] = 0 # 1 << ss
1518  sib_rez[index][tmp] += 1 << ss
1519  else:
1520  for rex_b in xrange(2):
1521  for rex_x in xrange(2):
1522  tmp = i + 8 * rex_x
1523  if i == 0b100 and rex_x == 0:
1524  continue
1525  if not tmp in sib_rez[rex_x][rex_b][index]:
1526  sib_rez[rex_x][rex_b][index][tmp] = 0 # 1 << ss
1527  sib_rez[rex_x][rex_b][index][tmp] += 1 << ss
1528 
1529  # 32bit
1530  db_afs_32 = [None for i in range(0x100)]
1531  for i in range(0x100):
1532  index = i
1533  mod, re, rm = getmodrm(i)
1534 
1535  if mod == 0b00:
1536  if rm == 0b100:
1537  db_afs_32[index] = sib_u32
1538  elif rm == 0b101:
1539  db_afs_32[index] = {f_isad: True, f_imm: f_u32}
1540  else:
1541  db_afs_32[index] = {f_isad: True, rm: 1}
1542  elif mod == 0b01:
1543  if rm == 0b100:
1544  db_afs_32[index] = sib_s08_ebp
1545  continue
1546  tmp = {f_isad: True, rm: 1, f_imm: f_s08}
1547  db_afs_32[index] = tmp
1548 
1549  elif mod == 0b10:
1550  if rm == 0b100:
1551  db_afs_32[index] = sib_u32_ebp
1552  else:
1553  db_afs_32[index] = {f_isad: True, rm: 1, f_imm: f_u32}
1554  elif mod == 0b11:
1555  db_afs_32[index] = {f_isad: False, rm: 1}
1556 
1557  # 64bit
1558  db_afs_64 = [None for i in range(0x400)]
1559  for i in range(0x400):
1560  index = i
1561  rex_x = (index >> 9) & 1
1562  rex_b = (index >> 8) & 1
1563  mod, re, rm = getmodrm(i & 0xff)
1564 
1565  if mod == 0b00:
1566  if rm == 0b100:
1567  db_afs_64[i] = sib_u64[rex_x][rex_b]
1568  elif rm == 0b101:
1569  db_afs_64[i] = {f_isad: True, f_imm: f_u32, 16: 1}
1570  else:
1571  db_afs_64[i] = {f_isad: True, rm + 8 * rex_b: 1}
1572  elif mod == 0b01:
1573  if rm == 0b100:
1574  db_afs_64[i] = sib_64_s08_ebp[rex_x][rex_b]
1575  continue
1576  tmp = {f_isad: True, rm + 8 * rex_b: 1, f_imm: f_s08}
1577  db_afs_64[i] = tmp
1578 
1579  elif mod == 0b10:
1580  if rm == 0b100:
1581  db_afs_64[i] = sib_u64_ebp[rex_x][rex_b]
1582  else:
1583  db_afs_64[i] = {f_isad: True, rm + 8 * rex_b: 1, f_imm: f_u32}
1584  elif mod == 0b11:
1585  db_afs_64[i] = {f_isad: False, rm + 8 * rex_b: 1}
1586 
1587  # 16bit
1588  db_afs_16 = [None for i in range(0x100)]
1589  _si = 6
1590  _di = 7
1591  _bx = 3
1592  _bp = 5
1593  for i in range(0x100):
1594  index = i
1595  mod, re, rm = getmodrm(i)
1596 
1597  if mod == 0b00:
1598  if rm == 0b100:
1599  db_afs_16[index] = {f_isad: True, _si: 1}
1600  elif rm == 0b101:
1601  db_afs_16[index] = {f_isad: True, _di: 1}
1602  elif rm == 0b110:
1603  db_afs_16[index] = {
1604  f_isad: True, f_imm: f_u16} # {f_isad:True,_bp:1}
1605  elif rm == 0b111:
1606  db_afs_16[index] = {f_isad: True, _bx: 1}
1607  else:
1608  db_afs_16[index] = {f_isad: True,
1609  [_si, _di][rm % 2]: 1,
1610  [_bx, _bp][(rm >> 1) % 2]: 1}
1611  elif mod in [0b01, 0b10]:
1612  if mod == 0b01:
1613  my_imm = f_s08
1614  else:
1615  my_imm = f_u16
1616 
1617  if rm == 0b100:
1618  db_afs_16[index] = {f_isad: True, _si: 1, f_imm: my_imm}
1619  elif rm == 0b101:
1620  db_afs_16[index] = {f_isad: True, _di: 1, f_imm: my_imm}
1621  elif rm == 0b110:
1622  db_afs_16[index] = {f_isad: True, _bp: 1, f_imm: my_imm}
1623  elif rm == 0b111:
1624  db_afs_16[index] = {f_isad: True, _bx: 1, f_imm: my_imm}
1625  else:
1626  db_afs_16[index] = {f_isad: True,
1627  [_si, _di][rm % 2]: 1,
1628  [_bx, _bp][(rm >> 1) % 2]: 1,
1629  f_imm: my_imm}
1630 
1631  elif mod == 0b11:
1632  db_afs_16[index] = {f_isad: False, rm: 1}
1633 
1634  byte2modrm = {}
1635  byte2modrm[16] = db_afs_16
1636  byte2modrm[32] = db_afs_32
1637  byte2modrm[64] = db_afs_64
1638 
1639  modrm2byte = {16: defaultdict(list),
1640  32: defaultdict(list),
1641  64: defaultdict(list),
1642  }
1643  for size, db_afs in byte2modrm.items():
1644  for i, modrm in enumerate(db_afs):
1645  if not isinstance(modrm, list):
1646  modrm = modrm.items()
1647  modrm.sort()
1648  modrm = tuple(modrm)
1649  modrm2byte[size][modrm].append(i)
1650  continue
1651  for j, modrm_f in enumerate(modrm):
1652  modrm_f = modrm_f.items()
1653  modrm_f.sort()
1654  modrm_f = tuple(modrm_f)
1655  modrm2byte[size][modrm_f].append((i, j))
1656 
1657  return byte2modrm, modrm2byte
1658 
1659 byte2modrm, modrm2byte = gen_modrm_form()
1660 
1661 
1662 # ret is modr; ret is displacement
1663 def exprfindmod(e, o=None):
1664  if o is None:
1665  o = {}
1666  if isinstance(e, ExprInt):
1667  return e
1668  if isinstance(e, ExprId):
1669  i = size2gpregs[e.size].expr.index(e)
1670  o[i] = 1
1671  return None
1672  elif isinstance(e, ExprOp):
1673  out = None
1674  if e.op == '+':
1675  for a in e.args:
1676  r = exprfindmod(a, o)
1677  if out and r1:
1678  raise ValueError('multiple displacement!')
1679  out = r
1680  return out
1681  elif e.op == "*":
1682  mul = int(e.args[1].arg)
1683  a = e.args[0]
1684  i = size2gpregs[a.size].expr.index(a)
1685  o[i] = mul
1686  else:
1687  raise ValueError('bad op')
1688  return None
1689 
1690 def test_addr_size(ptr, size):
1691  if isinstance(ptr, ExprInt):
1692  return ptr.arg < (1 << size)
1693  else:
1694  return ptr.size == size
1695 
1696 SIZE2XMMREG = {64:gpregs_mm,
1697  128:gpregs_xmm}
1698 
1699 def parse_mem(expr, parent, w8, sx=0, xmm=0, mm=0):
1700  dct_expr = {}
1701  opmode = parent.v_opmode()
1702  if expr.is_op_segm() and isinstance(expr.arg.args[0], ExprInt):
1703  return None, None, False
1704 
1705  if expr.is_op_segm():
1706  segm = expr.arg.args[0]
1707  ptr = expr.arg.args[1]
1708  else:
1709  segm = None
1710  ptr = expr.arg
1711 
1712  dct_expr[f_isad] = True
1713  ad_size = ptr.size
1714  admode = parent.v_admode()
1715  if not test_addr_size(ptr, admode):
1716  return None, None, False
1717 
1718  if (w8 == 1 and expr.size != opmode and not sx and
1719  not (hasattr(parent, 'sd') or hasattr(parent, 'wd'))):
1720  return None, None, False
1721 
1722  if hasattr(parent, 'wd'):
1723  if expr.size == 16:
1724  parent.wd.value = 1
1725  elif expr.size == 32:
1726  pass
1727  else:
1728  return None, None, False
1729 
1730  if (parent.mode == 64 and ptr.size == 32 and
1731  parent.admode != 1):
1732  return None, None, False
1733  dct_expr = {f_isad: True}
1734  disp = exprfindmod(ptr, dct_expr)
1735  out = []
1736  if disp is None:
1737  # add 0 disp
1738  disp = ExprInt32(0)
1739  if disp is not None:
1740  for signed, encoding, cast_int in [(True, f_s08, ExprInt8),
1741  (True, f_s16, ExprInt16),
1742  (True, f_s32, ExprInt32),
1743  (False, f_u08, ExprInt8),
1744  (False, f_u16, ExprInt16),
1745  (False, f_u32, ExprInt32)]:
1746  value = cast_int(int(disp.arg))
1747  if admode < value.size:
1748  if signed:
1749  if int(disp.arg) != sign_ext(int(value.arg), admode, disp.size):
1750  continue
1751  else:
1752  if int(disp.arg) != int(value.arg):
1753  continue
1754  else:
1755  if int(disp.arg) != sign_ext(int(value.arg), value.size, admode):
1756  continue
1757  x1 = dict(dct_expr)
1758  x1[f_imm] = (encoding, value)
1759  out.append(x1)
1760  else:
1761  out = [dct_expr]
1762  return out, segm, True
1763 
1764 def expr2modrm(expr, parent, w8, sx=0, xmm=0, mm=0):
1765  dct_expr = {f_isad : False}
1766 
1767  if mm or xmm:
1768  if mm and expr.size != 64:
1769  return None, None, False
1770  elif xmm and expr.size != 128:
1771  return None, None, False
1772 
1773  if isinstance(expr, ExprId):
1774  selreg = SIZE2XMMREG[expr.size]
1775  if not expr in selreg.expr:
1776  return None, None, False
1777  i = selreg.expr.index(expr)
1778  dct_expr[i] = 1
1779  return [dct_expr], None, True
1780  else:
1781  return parse_mem(expr, parent, w8, sx, xmm, mm)
1782 
1783  elif expr.size == 64 and expr not in gpregs_mm.expr:
1784  if hasattr(parent, 'sd'):
1785  parent.sd.value = 1
1786  elif hasattr(parent, 'wd'):
1787  pass
1788  elif hasattr(parent, 'stk'):
1789  pass
1790  else:
1791  parent.rex_w.value = 1
1792  opmode = parent.v_opmode()
1793  if sx == 1:
1794  opmode = 16
1795  if sx == 2:
1796  opmode = 32
1797  if expr.size == 8 and w8 != 0:
1798  return None, None, False
1799 
1800  if w8 == 0 and expr.size != 8:
1801  return None, None, False
1802 
1803  if not isinstance(expr, ExprMem):
1804  dct_expr[f_isad] = False
1805  if xmm:
1806  if expr in gpregs_xmm.expr:
1807  i = gpregs_xmm.expr.index(expr)
1808  dct_expr[i] = 1
1809  return [dct_expr], None, True
1810  else:
1811  return None, None, False
1812  if mm:
1813  if expr in gpregs_mm.expr:
1814  i = gpregs_mm.expr.index(expr)
1815  dct_expr[i] = 1
1816  return [dct_expr], None, True
1817  else:
1818  return None, None, False
1819  if w8 == 0:
1820  if parent.mode == 64 and expr in gpregs08_64.expr:
1821  r = gpregs08_64
1822  parent.rex_p.value = 1
1823  else:
1824  parent.rex_p.value = 0
1825  parent.rex_x.value = 0
1826  r = size2gpregs[8]
1827  if not expr in r.expr:
1828  return None, None, False
1829  i = r.expr.index(expr)
1830  dct_expr[i] = 1
1831  return [dct_expr], None, True
1832  if opmode != expr.size:
1833  return None, None, False
1834  if not expr in size2gpregs[opmode].expr:
1835  return None, None, False
1836  i = size2gpregs[opmode].expr.index(expr)
1837  if i > 7:
1838  if parent.mode != 64:
1839  return None, None, False
1840  dct_expr[i] = 1
1841  return [dct_expr], None, True
1842  return parse_mem(expr, parent, w8, sx, xmm, mm)
1843 
1844 def modrm2expr(modrm, parent, w8, sx=0, xmm=0, mm=0):
1845  o = []
1846  if not modrm[f_isad]:
1847  modrm_k = [x[0] for x in modrm.iteritems() if x[1] == 1]
1848  if len(modrm_k) != 1:
1849  raise ValueError('strange reg encoding %r' % modrm)
1850  modrm_k = modrm_k[0]
1851  if w8 == 0:
1852  opmode = 8
1853  elif sx == 1:
1854  opmode = 16
1855  elif sx == 2:
1856  opmode = 32
1857  else:
1858  opmode = parent.v_opmode()
1859  if xmm:
1860  expr = gpregs_xmm.expr[modrm_k]
1861  elif mm:
1862  expr = gpregs_mm.expr[modrm_k]
1863  elif opmode == 8 and (parent.v_opmode() == 64 or parent.rex_p.value == 1):
1864  expr = gpregs08_64.expr[modrm_k]
1865  else:
1866  expr = size2gpregs[opmode].expr[modrm_k]
1867  return expr
1868  admode = parent.v_admode()
1869  opmode = parent.v_opmode()
1870  for modrm_k, scale in modrm.items():
1871  if isinstance(modrm_k, (int, long)):
1872  expr = size2gpregs[admode].expr[modrm_k]
1873  if scale != 1:
1874  expr = ExprInt(scale, admode) * expr
1875  o.append(expr)
1876  if f_imm in modrm:
1877  if parent.disp.value is None:
1878  return None
1879  o.append(ExprInt(int(parent.disp.expr.arg), admode))
1880  expr = ExprOp('+', *o)
1881  if w8 == 0:
1882  opmode = 8
1883  elif sx == 1:
1884  opmode = 16
1885  elif sx == 2:
1886  opmode = 32
1887  if xmm:
1888  opmode = 128
1889  elif mm:
1890  opmode = 64
1891 
1892  expr = ExprMem(expr, size=opmode)
1893  return expr
1894 
1895 
1897  parser = rmarg
1898 
1899  def fromstring(self, s, parser_result=None):
1900  start, stop = super(x86_rm_arg, self).fromstring(s, parser_result)
1901  p = self.parent
1902  if start is None:
1903  return None, None
1904  s = self.expr.size
1905  return start, stop
1906 
1907  def get_modrm(self):
1908  p = self.parent
1909  admode = p.v_admode()
1910 
1911  if not admode in [16, 32, 64]:
1912  raise ValueError('strange admode %r', admode)
1913  v = setmodrm(p.mod.value, 0, p.rm.value)
1914  v |= p.rex_b.value << 8
1915  v |= p.rex_x.value << 9
1916  if p.mode == 64:
1917  # XXXx to check
1918  admode = 64
1919 
1920  xx = byte2modrm[admode][v]
1921  if isinstance(xx, list):
1922  if not p.sib_scale:
1923  return False
1924  v = setmodrm(p.sib_scale.value,
1925  p.sib_index.value,
1926  p.sib_base.value)
1927  xx = xx[v]
1928  return xx
1929 
1930  def decode(self, v):
1931  p = self.parent
1932  xx = self.get_modrm()
1933  self.expr = modrm2expr(xx, p, 1)
1934  return self.expr is not None
1935 
1936  def gen_cand(self, v_cand, admode):
1937  if not admode in modrm2byte:
1938  # XXX TODO: 64bit
1939  raise StopIteration
1940  if not v_cand:
1941  raise StopIteration
1942 
1943  p = self.parent
1944  o_rex_x = p.rex_x.value
1945  o_rex_b = p.rex_b.value
1946  # add candidate without 0 imm
1947  new_v_cand = []
1948  moddd = False
1949  for v in v_cand:
1950  new_v_cand.append(v)
1951  if f_imm in v and int(v[f_imm][1].arg) == 0:
1952  v = dict(v)
1953  del(v[f_imm])
1954  new_v_cand.append(v)
1955  moddd = True
1956 
1957  v_cand = new_v_cand
1958 
1959  out_c = []
1960  for v in v_cand:
1961  disp = None
1962  # patch value in modrm
1963  if f_imm in v:
1964  size, disp = v[f_imm]
1965  disp = int(disp.arg)
1966 
1967  v[f_imm] = size
1968  vo = v
1969  v = v.items()
1970  v.sort()
1971  v = tuple(v)
1972  if not v in modrm2byte[admode]:
1973  continue
1974  xx = modrm2byte[admode][v]
1975 
1976  # default case
1977  for x in xx:
1978  if type(x) == tuple:
1979  modrm, sib = x
1980  else:
1981  modrm = x
1982  sib = None
1983 
1984  # 16 bit cannot have sib
1985  if (not sib is None) and admode == 16:
1986  continue
1987  rex = modrm >> 8 # 0# XXX HACK REM temporary REX modrm>>8
1988  if rex and admode != 64:
1989  continue
1990 
1991  p.rex_x.value = (rex >> 1) & 1
1992  p.rex_b.value = rex & 1
1993 
1994  if o_rex_x is not None and p.rex_x.value != o_rex_x:
1995  continue
1996  if o_rex_b is not None and p.rex_b.value != o_rex_b:
1997  continue
1998 
1999  mod, re, rm = getmodrm(modrm)
2000  # check re on parent
2001  if re != p.reg.value:
2002  continue
2003 
2004  if sib:
2005  s_scale, s_index, s_base = getmodrm(sib)
2006  else:
2007  s_scale, s_index, s_base = None, None, None
2008 
2009  p.mod.value = mod
2010  p.rm.value = rm
2011  p.sib_scale.value = s_scale
2012  p.sib_index.value = s_index
2013  p.sib_base.value = s_base
2014  p.disp.value = disp
2015  if disp is not None:
2016  p.disp.l = f_imm2size[vo[f_imm]]
2017 
2018  yield True
2019 
2020  raise StopIteration
2021 
2022  def encode(self):
2023  if isinstance(self.expr, ExprInt):
2024  raise StopIteration
2025  p = self.parent
2026  admode = p.v_admode()
2027  mode = self.expr.size
2028  v_cand, segm, ok = expr2modrm(self.expr, p, 1)
2029  if segm:
2030  p.g2.value = segm2enc[segm]
2031  for x in self.gen_cand(v_cand, admode):
2032  yield x
2033 
2034 
2036 
2037  def decode(self, v):
2038  p = self.parent
2039  xx = self.get_modrm()
2040  self.expr = modrm2expr(xx, p, p.w8.value)
2041  return self.expr is not None
2042 
2043  def encode(self):
2044  if isinstance(self.expr, ExprInt):
2045  raise StopIteration
2046  p = self.parent
2047  if p.w8.value is None:
2048  if self.expr.size == 8:
2049  p.w8.value = 0
2050  else:
2051  p.w8.value = 1
2052 
2053  v_cand, segm, ok = expr2modrm(self.expr, p, p.w8.value)
2054  if segm:
2055  p.g2.value = segm2enc[segm]
2056  for x in self.gen_cand(v_cand, p.v_admode()):
2057  yield x
2058 
2059 
2061 
2062  def decode(self, v):
2063  p = self.parent
2064  xx = self.get_modrm()
2065  self.expr = modrm2expr(xx, p, p.w8.value, 1)
2066  return self.expr is not None
2067 
2068  def encode(self):
2069  if isinstance(self.expr, ExprInt):
2070  raise StopIteration
2071  p = self.parent
2072  if p.w8.value is None:
2073  if self.expr.size == 8:
2074  p.w8.value = 0
2075  else:
2076  p.w8.value = 1
2077  v_cand, segm, ok = expr2modrm(self.expr, p, p.w8.value, 1)
2078  if segm:
2079  p.g2.value = segm2enc[segm]
2080  for x in self.gen_cand(v_cand, p.v_admode()):
2081  yield x
2082 
2083 
2085 
2086  def decode(self, v):
2087  p = self.parent
2088  xx = self.get_modrm()
2089  self.expr = modrm2expr(xx, p, 1, 2)
2090  return self.expr is not None
2091 
2092  def encode(self):
2093  if isinstance(self.expr, ExprInt):
2094  raise StopIteration
2095  p = self.parent
2096  v_cand, segm, ok = expr2modrm(self.expr, p, 1, 2)
2097  if segm:
2098  p.g2.value = segm2enc[segm]
2099  for x in self.gen_cand(v_cand, p.v_admode()):
2100  yield x
2101 
2102 
2104  out_size = 64
2105  def get_s_value(self):
2106  return self.parent.sd.value
2107  def set_s_value(self, value):
2108  self.parent.sd.value = value
2109 
2110  def decode(self, v):
2111  p = self.parent
2112  xx = self.get_modrm()
2113  expr = modrm2expr(xx, p, 1)
2114  if not isinstance(expr, ExprMem):
2115  return False
2116  if self.get_s_value() == 0:
2117  expr = ExprMem(expr.arg, 32)
2118  else:
2119  expr = ExprMem(expr.arg, self.out_size)
2120  self.expr = expr
2121  return self.expr is not None
2122 
2123  def encode(self):
2124  if isinstance(self.expr, ExprInt):
2125  raise StopIteration
2126  p = self.parent
2127  if not self.expr.size in [32, 64]:
2128  raise StopIteration
2129  self.set_s_value(0)
2130  v_cand, segm, ok = expr2modrm(self.expr, p, 1)
2131  for x in self.gen_cand(v_cand, p.v_admode()):
2132  yield x
2133 
2134 
2136  out_size = 16
2137  def get_s_value(self):
2138  return self.parent.wd.value
2139  def set_s_value(self, value):
2140  self.parent.wd.value = value
2141 
2142  def encode(self):
2143  if isinstance(self.expr, ExprInt):
2144  raise StopIteration
2145  p = self.parent
2146  p.wd.value = 0
2147  v_cand, segm, ok = expr2modrm(self.expr, p, 1)
2148  for x in self.gen_cand(v_cand, p.v_admode()):
2149  yield x
2150 
2151 
2153  msize = 64
2154 
2155  def decode(self, v):
2156  p = self.parent
2157  xx = self.get_modrm()
2158  expr = modrm2expr(xx, p, 1)
2159  if not isinstance(expr, ExprMem):
2160  return False
2161  self.expr = ExprMem(expr.arg, self.msize)
2162  return self.expr is not None
2163 
2164  def encode(self):
2165  if isinstance(self.expr, ExprInt):
2166  raise StopIteration
2167  p = self.parent
2168  v_cand, segm, ok = expr2modrm(self.expr, p, 0, 0, 0, 1)
2169  for x in self.gen_cand(v_cand, p.v_admode()):
2170  yield x
2171 
2172 
2174  msize = 80
2175 
2176  def encode(self):
2177  if isinstance(self.expr, ExprInt):
2178  raise StopIteration
2179  if not isinstance(self.expr, ExprMem) or self.expr.size != self.msize:
2180  raise StopIteration
2181  p = self.parent
2182  mode = p.mode
2183  if mode == 64:
2184  mode = 32
2185  self.expr = ExprMem(self.expr.arg, mode)
2186  v_cand, segm, ok = expr2modrm(self.expr, p, 1)
2187  for x in self.gen_cand(v_cand, p.v_admode()):
2188  yield x
2189 
2190 
2192  msize = 8
2193 
2194  def decode(self, v):
2195  p = self.parent
2196  xx = self.get_modrm()
2197  self.expr = modrm2expr(xx, p, 0)
2198  return self.expr is not None
2199 
2200  def encode(self):
2201  if self.expr.size != 8:
2202  raise StopIteration
2203  p = self.parent
2204  mode = p.mode
2205  v_cand, segm, ok = expr2modrm(self.expr, p, 0)
2206  for x in self.gen_cand(v_cand, p.v_admode()):
2207  yield x
2208 
2209 
2211  msize = 16
2212 
2213 
2215  msize = 64
2216  is_mm = True
2217  is_xmm = False
2218 
2219  def decode(self, v):
2220  p = self.parent
2221  xx = self.get_modrm()
2222  expr = modrm2expr(xx, p, 0, 0, self.is_xmm, self.is_mm)
2223  if isinstance(expr, ExprMem) and expr.size != self.msize:
2224  expr = ExprMem(expr.arg, self.msize)
2225  self.expr = expr
2226  return True
2227 
2228 
2229  def encode(self):
2230  expr = self.expr
2231  if isinstance(expr, ExprInt):
2232  raise StopIteration
2233  if isinstance(expr, ExprMem) and expr.size != self.msize:
2234  raise StopIteration
2235  p = self.parent
2236  mode = p.mode
2237  if mode == 64:
2238  mode = 32
2239  if isinstance(expr, ExprMem):
2240  if self.is_xmm:
2241  expr = ExprMem(expr.arg, 128)
2242  elif self.is_mm:
2243  expr = ExprMem(expr.arg, 64)
2244 
2245  v_cand, segm, ok = expr2modrm(expr, p, 0, 0, self.is_xmm, self.is_mm)
2246  for x in self.gen_cand(v_cand, p.v_admode()):
2247  yield x
2248 
2249 
2251  msize = 64
2252  is_mm = True
2253  is_xmm = False
2254 
2256  msize = 128
2257  is_mm = False
2258  is_xmm = True
2259 
2260 
2262  msize = 32
2263  is_mm = False
2264  is_xmm = True
2265 
2267  msize = 64
2268  is_mm = False
2269  is_xmm = True
2270 
2271 
2273  prio = default_prio + 1
2274 
2275  parser = gpreg
2276 
2277  def fromstring(self, s, parser_result=None):
2278  if not hasattr(self.parent, 'sx') and hasattr(self.parent, "w8"):
2279  self.parent.w8.value = 1
2280  if parser_result:
2281  e, start, stop = parser_result[self.parser]
2282  if e is None:
2283  return None, None
2284  self.expr = e
2285  if self.expr.size == 8:
2286  if hasattr(self.parent, 'sx') or not hasattr(self.parent, 'w8'):
2287  return None, None
2288  self.parent.w8.value = 0
2289  return start, stop
2290  try:
2291  v, start, stop = self.parser.scanString(s).next()
2292  except StopIteration:
2293  return None, None
2294  self.expr = v[0]
2295  if self.expr.size == 0:
2296  if hasattr(self.parent, 'sx') or not hasattr(self.parent, 'w8'):
2297  return None, None
2298  self.parent.w8.value = 0
2299 
2300  return start, stop
2301 
2302  def getrexsize(self):
2303  return self.parent.rex_r.value
2304 
2305  def setrexsize(self, v):
2306  self.parent.rex_r.value = v
2307 
2308  def decode(self, v):
2309  v = v & self.lmask
2310  p = self.parent
2311  opmode = p.v_opmode()
2312  if not hasattr(p, 'sx') and (hasattr(p, 'w8') and p.w8.value == 0):
2313  opmode = 8
2314  r = size2gpregs[opmode]
2315  if p.mode == 64 and self.getrexsize():
2316  v |= 0x8
2317  if p.v_opmode() == 64 or p.rex_p.value == 1:
2318  if not hasattr(p, 'sx') and (hasattr(p, 'w8') and p.w8.value == 0):
2319  r = gpregs08_64
2320  self.expr = r.expr[v]
2321  return True
2322 
2323  def encode(self):
2324  if not isinstance(self.expr, ExprId):
2325  return False
2326  if self.expr in gpregs64.expr and not hasattr(self.parent, 'stk'):
2327  self.parent.rex_w.value = 1
2328  opmode = self.parent.v_opmode()
2329  if not hasattr(self.parent, 'sx') and hasattr(self.parent, 'w8'):
2330  self.parent.w8.value = 1
2331  if self.expr.size == 8:
2332  if hasattr(self.parent, 'sx') or not hasattr(self.parent, 'w8'):
2333  return False
2334  self.parent.w8.value = 0
2335  opmode = 8
2336  r = size2gpregs[opmode]
2337  if self.expr in r.expr:
2338  i = r.expr.index(self.expr)
2339  elif (opmode == 8 and self.parent.mode == 64 and
2340  self.expr in gpregs08_64.expr):
2341  i = gpregs08_64.expr.index(self.expr)
2342  self.parent.rex_p.value = 1
2343  else:
2344  log.debug("cannot encode reg %r", self.expr)
2345  return False
2346  if self.parent.v_opmode() == 64:
2347  if i > 7:
2348  self.setrexsize(1)
2349  i -= 8
2350  elif self.parent.mode == 64 and i > 7:
2351  i -= 8
2352  self.setrexsize(1)
2353  self.value = i
2354  if self.value > self.lmask:
2355  log.debug("cannot encode field value %x %x",
2356  self.value, self.lmask)
2357  return False
2358  return True
2359 
2360 
2362  selreg = gpregs_mm
2363  def decode(self, v):
2364  if self.parent.mode == 64 and self.getrexsize():
2365  v |= 0x8
2366  self.expr = self.selreg.expr[v]
2367  return True
2368 
2369  def encode(self):
2370  if not isinstance(self.expr, ExprId):
2371  return False
2372  if self.expr not in self.selreg.expr:
2373  return False
2374  i = self.selreg.expr.index(self.expr)
2375  if self.parent.mode == 64 and i > 7:
2376  i -= 8
2377  self.setrexsize(1)
2378  self.value = i
2379  if self.value > self.lmask:
2380  log.debug("cannot encode field value %x %x",
2381  self.value, self.lmask)
2382  return False
2383  return True
2384 
2386  selreg = gpregs_xmm
2387 
2389  pass
2390 
2391 
2392 class x86_reg(x86_rm_reg):
2393 
2394  def getrexsize(self):
2395  return self.parent.rex_b.value
2396 
2397  def setrexsize(self, v):
2398  self.parent.rex_b.value = v
2399 
2400 
2402 
2403  def getrexsize(self):
2404  return self.parent.rex_b.value
2405 
2406  def setrexsize(self, v):
2407  self.parent.rex_b.value = v
2408 
2409 
2411  prio = default_prio + 1
2412  reg_info = segmreg
2413  parser = reg_info.parser
2414 
2415 
2417  prio = default_prio + 1
2418  reg_info = crregs
2419  parser = reg_info.parser
2420 
2421 
2423  prio = default_prio + 1
2424  reg_info = drregs
2425  parser = reg_info.parser
2426 
2427 
2429  prio = default_prio + 1
2430  reg_info = fltregs
2431  parser = reg_info.parser
2432 
2433 
2434 class bs_fbit(bsi):
2435 
2436  def decode(self, v):
2437  # value already decoded in pre_dis_info
2438  return True
2439 
2440 
2441 class bs_cl1(bsi, m_arg):
2442  parser = cl_or_imm
2443 
2444  def decode(self, v):
2445  if v == 1:
2446  self.expr = regs08_expr[1]
2447  else:
2448  self.expr = ExprInt8(1)
2449  return True
2450 
2451  def encode(self):
2452  if self.expr == regs08_expr[1]:
2453  self.value = 1
2454  elif isinstance(self.expr, ExprInt) and int(self.expr.arg) == 1:
2455  self.value = 0
2456  else:
2457  return False
2458  return True
2459 
2460 
2461 def sib_cond(cls, mode, v):
2462  if admode_prefix((mode, v["opmode"], v["admode"])) == 16:
2463  return None
2464  if v['mod'] == 0b11:
2465  return None
2466  elif v['rm'] == 0b100:
2467  return cls.ll
2468  else:
2469  return None
2470  return v['rm'] == 0b100
2471 
2472 
2474  # cond must return field len
2475  ll = 2
2476 
2477  @classmethod
2478  def flen(cls, mode, v):
2479  return sib_cond(cls, mode, v)
2480 
2481  def encode(self):
2482  if self.value is None:
2483  self.value = 0
2484  self.l = 0
2485  return True
2486  return super(bs_cond_scale, self).encode()
2487 
2488  def decode(self, v):
2489  self.value = v
2490  return True
2491 
2492 
2494  ll = 3
2495 
2496  @classmethod
2497  def flen(cls, mode, v):
2498  return sib_cond(cls, mode, v)
2499 
2500 
2502  # cond must return field len
2503 
2504  @classmethod
2505  def flen(cls, mode, v):
2506  if admode_prefix((mode, v['opmode'], v['admode'])) == 16:
2507  if v['mod'] == 0b00:
2508  if v['rm'] == 0b110:
2509  return 16
2510  else:
2511  return None
2512  elif v['mod'] == 0b01:
2513  return 8
2514  elif v['mod'] == 0b10:
2515  return 16
2516  return None
2517  # 32, 64
2518  if 'sib_base' in v and v['sib_base'] == 0b101:
2519  if v['mod'] == 0b00:
2520  return 32
2521  elif v['mod'] == 0b01:
2522  return 8
2523  elif v['mod'] == 0b10:
2524  return 32
2525  else:
2526  return None
2527 
2528  if v['mod'] == 0b00:
2529  if v['rm'] == 0b101:
2530  return 32
2531  else:
2532  return None
2533  elif v['mod'] == 0b01:
2534  return 8
2535  elif v['mod'] == 0b10:
2536  return 32
2537  else:
2538  return None
2539 
2540  def encode(self):
2541  if self.value is None:
2542  self.value = 0
2543  self.l = 0
2544  return True
2545  self.value = swap_uint(self.l, self.value)
2546  return True
2547 
2548  def decode(self, v):
2549  admode = self.parent.v_admode()
2550  v = swap_uint(self.l, v)
2551  self.value = v
2552  v = sign_ext(v, self.l, admode)
2553  v = ExprInt(v, admode)
2554  self.expr = v
2555  return True
2556 
2557 
2559  parser = int_or_expr
2560  max_size = 32
2561 
2562  def fromstring(self, s, parser_result=None):
2563  if parser_result:
2564  expr, start, stop = parser_result[self.parser]
2565  else:
2566  try:
2567  expr, start, stop = self.parser.scanString(s).next()
2568  except StopIteration:
2569  expr = None
2570  self.expr = expr
2571 
2572  if len(self.parent.args) > 1:
2573  l = self.parent.args[0].expr.size
2574  else:
2575  l = self.parent.v_opmode()
2576  if isinstance(self.expr, ExprInt):
2577  v = int(self.expr.arg)
2578  mask = ((1 << l) - 1)
2579  self.expr = ExprInt(v & mask, l)
2580 
2581  if self.expr is None:
2582  log.debug('cannot fromstring int %r', s)
2583  return None, None
2584  return start, stop
2585 
2586  @classmethod
2587  def flen(cls, mode, v):
2588  if 'w8' not in v or v['w8'] == 1:
2589  if 'se' in v and v['se'] == 1:
2590  return 8
2591  else:
2592  osize = v_opmode_info(mode, v['opmode'], v['rex_w'], 0)
2593  osize = min(osize, cls.max_size)
2594  return osize
2595  return 8
2596 
2597  def getmaxlen(self):
2598  return 32
2599 
2600  def encode(self):
2601  if not isinstance(self.expr, ExprInt):
2602  raise StopIteration
2603  arg0_expr = self.parent.args[0].expr
2604  self.parent.rex_w.value = 0
2605  # special case for push
2606  if len(self.parent.args) == 1:
2607  v = int(self.expr.arg)
2608  l = self.parent.v_opmode()
2609  l = min(l, self.max_size)
2610 
2611  self.l = l
2612  mask = ((1 << self.l) - 1)
2613  if v != sign_ext(v & mask, self.l, l):
2614  raise StopIteration
2615  self.value = swap_uint(self.l, v & ((1 << self.l) - 1))
2616  yield True
2617  raise StopIteration
2618 
2619  # assume 2 args; use first arg to guess op size
2620  if arg0_expr.size == 64:
2621  self.parent.rex_w.value = 1
2622 
2623  l = self.parent.v_opmode()
2624  v = int(self.expr.arg)
2625  if arg0_expr.size == 8:
2626  if not hasattr(self.parent, 'w8'):
2627  raise StopIteration
2628  self.parent.w8.value = 0
2629  l = 8
2630  if hasattr(self.parent, 'se'):
2631  self.parent.se.value = 0
2632  elif hasattr(self.parent, 'se'):
2633  if hasattr(self.parent, 'w8'):
2634  self.parent.w8.value = 1
2635  # try to generate signed extended version
2636  if v == sign_ext(v & 0xFF, 8, arg0_expr.size):
2637  self.parent.se.value = 1
2638  self.l = 8
2639  self.value = v & 0xFF
2640  yield True
2641  self.parent.se.value = 0
2642  else:
2643  if hasattr(self.parent, 'w8'):
2644  self.parent.w8.value = 1
2645  if l == 64:
2646  self.l = self.getmaxlen()
2647  else:
2648  self.l = l
2649 
2650  mask = ((1 << self.l) - 1)
2651  if v != sign_ext(v & mask, self.l, l):
2652  raise StopIteration
2653  self.value = swap_uint(self.l, v & ((1 << self.l) - 1))
2654  yield True
2655 
2656  def decode(self, v):
2657  opmode = self.parent.v_opmode()
2658  v = swap_uint(self.l, v)
2659  self.value = v
2660  l_out = opmode
2661  if hasattr(self.parent, 'w8') and self.parent.w8.value == 0:
2662  l_out = 8
2663  v = sign_ext(v, self.l, l_out)
2664  self.expr = ExprInt(v, l_out)
2665  return True
2666 
2667 
2669  max_size = 64
2670 
2671  def getmaxlen(self):
2672  return 64
2673 
2674  @classmethod
2675  def flen(cls, mode, v):
2676  if 'w8' not in v or v['w8'] == 1:
2677  if 'se' in v and v['se'] == 1:
2678  return 8
2679  else:
2680  osize = v_opmode_info(mode, v['opmode'], v['rex_w'], 0)
2681  return osize
2682  else:
2683  return 8
2684 
2685 
2687  parser = int_or_expr
2688 
2689  def fromstring(self, s, parser_result=None):
2690  if parser_result:
2691  expr, start, stop = parser_result[self.parser]
2692  else:
2693  try:
2694  expr, start, stop = self.parser.scanString(s).next()
2695  except StopIteration:
2696  expr = None
2697  self.expr = expr
2698  l = self.parent.mode
2699  if isinstance(self.expr, ExprInt):
2700  v = int(self.expr.arg)
2701  mask = ((1 << l) - 1)
2702  self.expr = ExprInt(v & mask, l)
2703  return start, stop
2704 
2705  @classmethod
2706  def flen(cls, mode, v):
2707  osize = v_opmode_info(mode, v['opmode'], v['rex_w'], 0)
2708  if osize == 16:
2709  return 16
2710  else:
2711  return 32
2712 
2713  def encode(self):
2714  if not isinstance(self.expr, ExprInt):
2715  raise StopIteration
2716  arg0_expr = self.parent.args[0].expr
2717  if self.l != 0:
2718  l = self.l
2719  else:
2720  l = self.parent.v_opmode()
2721  self.l = l
2722  l = offsize(self.parent)
2723  prefix = self.parent.gen_prefix()
2724  parent_len = len(prefix) * 8 + self.parent.l + self.l
2725  assert(parent_len % 8 == 0)
2726 
2727  v = int(self.expr.arg - parent_len/8)
2728  if prefix is None:
2729  raise StopIteration
2730  mask = ((1 << self.l) - 1)
2731  if self.l > l:
2732  raise StopIteration
2733  if v != sign_ext(v & mask, self.l, l):
2734  raise StopIteration
2735  self.value = swap_uint(self.l, v & ((1 << self.l) - 1))
2736  yield True
2737 
2738  def decode(self, v):
2739  v = swap_uint(self.l, v)
2740  size = offsize(self.parent)
2741  v = sign_ext(v, self.l, size)
2742  v += self.parent.l
2743  self.expr = ExprInt(v, size)
2744  return True
2745 
2747  parser = int_or_expr
2748 
2749  @classmethod
2750  def flen(cls, mode, v):
2751  return 8
2752 
2753  def encode(self):
2754  if not isinstance(self.expr, ExprInt):
2755  raise StopIteration
2756  arg0_expr = self.parent.args[0].expr
2757  if self.l != 0:
2758  l = self.l
2759  else:
2760  l = self.parent.v_opmode()
2761  self.l = l
2762  l = offsize(self.parent)
2763  v = int(self.expr.arg)
2764  mask = ((1 << self.l) - 1)
2765  if self.l > l:
2766  raise StopIteration
2767  if v != sign_ext(v & mask, self.l, l):
2768  raise StopIteration
2769  self.value = swap_uint(self.l, v & ((1 << self.l) - 1))
2770  yield True
2771 
2772  def decode(self, v):
2773  v = swap_uint(self.l, v)
2774  size = offsize(self.parent)
2775  v = sign_ext(v, self.l, size)
2776  self.expr = ExprInt(v, size)
2777  return True
2778 
2779 
2781 
2782  @classmethod
2783  def flen(cls, mode, v):
2784  return 8
2785 
2786 
2787 class bs_moff(bsi):
2788 
2789  @classmethod
2790  def flen(cls, mode, v):
2791  osize = v_opmode_info(mode, v['opmode'], v['rex_w'], 0)
2792  if osize == 16:
2793  return 16
2794  else:
2795  return 32
2796 
2797  def encode(self):
2798  if not hasattr(self.parent, "mseg"):
2799  raise StopIteration
2800  m = self.parent.mseg.expr
2801  if not (isinstance(m, ExprOp) and m.op == 'segm'):
2802  raise StopIteration
2803  if not isinstance(m.args[1], ExprInt):
2804  raise StopIteration
2805  l = self.parent.v_opmode()
2806  if l == 16:
2807  self.l = 16
2808  else:
2809  self.l = 32
2810  v = int(m.args[1].arg)
2811  mask = ((1 << self.l) - 1)
2812  if v != sign_ext(v & mask, self.l, l):
2813  raise StopIteration
2814  self.value = swap_uint(self.l, v & ((1 << self.l) - 1))
2815  yield True
2816 
2817  def decode(self, v):
2818  opmode = self.parent.v_opmode()
2819  if opmode == 64:
2820  return False
2821  v = swap_uint(self.l, v)
2822  self.value = v
2823  v = sign_ext(v, self.l, opmode)
2824  self.expr = ExprInt(v, opmode)
2825  return True
2826 
2827 
2829  parser = deref_mem
2830 
2831  def fromstring(self, s, parser_result=None):
2832  if parser_result:
2833  e, start, stop = parser_result[self.parser]
2834  if e is None:
2835  return None, None
2836  if not isinstance(e, ExprMem):
2837  return None, None
2838  self.expr = e
2839  if self.expr is None:
2840  return None, None
2841  return start, stop
2842  try:
2843  v, start, stop = self.parser.scanString(s).next()
2844  except StopIteration:
2845  return None, None
2846  if not isinstance(e, ExprMem):
2847  return None, None
2848  self.expr = v[0]
2849  if self.expr is None:
2850  log.debug('cannot fromstring int %r', s)
2851  return None, None
2852  return start, stop
2853 
2854  @classmethod
2855  def flen(cls, mode, v):
2856  if mode == 64:
2857  if v['admode']:
2858  return 32
2859  else:
2860  return 64
2861  asize = v_admode_info(mode, v['admode'])
2862  return asize
2863 
2864  def encode(self):
2865  p = self.parent
2866  if not isinstance(self.expr, ExprMem) or not isinstance(self.expr.arg, ExprInt):
2867  raise StopIteration
2868  self.l = p.v_admode()
2869  v = int(self.expr.arg.arg)
2870  mask = ((1 << self.l) - 1)
2871  if v != mask & v:
2872  raise StopIteration
2873  self.value = swap_uint(self.l, v & ((1 << self.l) - 1))
2874  yield True
2875 
2876  def decode(self, v):
2877  if self.parent.mode == 64:
2878  if self.parent.admode == 1:
2879  l = 32
2880  else:
2881  l = 64
2882  else:
2883  l = self.parent.v_admode()
2884  v = swap_uint(self.l, v)
2885  self.value = v
2886  v = sign_ext(v, self.l, l)
2887  v = ExprInt(v, l)
2888  size = self.parent.v_opmode()
2889  if self.parent.w8.value == 0:
2890  size = 8
2891  self.expr = ExprMem(v, size)
2892  return True
2893 
2894 
2896  parser = deref_ptr
2897 
2898  def fromstring(self, s, parser_result=None):
2899  if parser_result:
2900  e, start, stop = parser_result[self.parser]
2901  if e is None:
2902  return None, None
2903  self.expr = e
2904  if self.expr is None:
2905  return None, None
2906  return start, stop
2907  try:
2908  v, start, stop = self.parser.scanString(s).next()
2909  except StopIteration:
2910  return None, None
2911  self.expr = v[0]
2912  if self.expr is None:
2913  log.debug('cannot fromstring int %r', s)
2914  return None, None
2915  return start, stop
2916 
2917  def encode(self):
2918  if not (isinstance(self.expr, ExprOp) and self.expr.op == 'segm'):
2919  raise StopIteration
2920  if not isinstance(self.expr.args[0], ExprInt):
2921  raise StopIteration
2922  if not isinstance(self.expr.args[1], ExprInt):
2923  raise StopIteration
2924  l = self.parent.v_opmode()
2925  v = int(self.expr.args[0].arg)
2926  mask = ((1 << self.l) - 1)
2927  if v != sign_ext(v & mask, self.l, l):
2928  raise StopIteration
2929  self.value = swap_uint(self.l, v & ((1 << self.l) - 1))
2930  yield True
2931 
2932  def decode(self, v):
2933  opmode = self.parent.v_opmode()
2934  v = swap_uint(self.l, v)
2935  self.value = v
2936  v = ExprInt16(v)
2937  self.expr = ExprOp('segm', v, self.parent.off.expr)
2938  return True
2939 
2940 
2941 d_rex_p = bs(l=0, cls=(bs_fbit,), fname="rex_p")
2942 d_rex_w = bs(l=0, cls=(bs_fbit,), fname="rex_w")
2943 d_rex_r = bs(l=0, cls=(bs_fbit,), fname="rex_r")
2944 d_rex_x = bs(l=0, cls=(bs_fbit,), fname="rex_x")
2945 d_rex_b = bs(l=0, cls=(bs_fbit,), fname="rex_b")
2946 
2947 d_g1 = bs(l=0, cls=(bs_fbit,), fname="g1")
2948 d_g2 = bs(l=0, cls=(bs_fbit,), fname="g2")
2949 
2950 
2951 d_cl1 = bs(l=1, cls=(bs_cl1,), fname="cl1")
2952 
2953 
2954 w8 = bs(l=1, fname="w8")
2955 se = bs(l=1, fname="se")
2956 
2957 sx = bs(l=0, fname="sx")
2958 sxd = bs(l=0, fname="sx")
2959 
2960 
2961 xmmreg = bs(l=0, fname="xmmreg")
2962 mmreg = bs(l=0, fname="mmreg")
2963 
2964 pref_f2 = bs(l=0, fname="prefixed", default="\xf2")
2965 pref_f3 = bs(l=0, fname="prefixed", default="\xf3")
2966 pref_66 = bs(l=0, fname="prefixed", default="\x66")
2967 no_xmm_pref = bs(l=0, fname="no_xmm_pref")
2968 
2969 sib_scale = bs(l=2, cls=(bs_cond_scale,), fname = "sib_scale")
2970 sib_index = bs(l=3, cls=(bs_cond_index,), fname = "sib_index")
2971 sib_base = bs(l=3, cls=(bs_cond_index,), fname = "sib_base")
2972 
2973 disp = bs(l=0, cls=(bs_cond_disp,), fname = "disp")
2974 
2975 s08 = bs(l=8, cls=(bs_s08, ))
2976 
2977 u08 = bs(l=8, cls=(x86_08, m_arg))
2978 u07 = bs(l=7, cls=(x86_08, m_arg))
2979 u16 = bs(l=16, cls=(x86_16, m_arg))
2980 u32 = bs(l=32, cls=(x86_32, m_arg))
2981 s3264 = bs(l=32, cls=(x86_s32to64, m_arg))
2982 
2983 u08_3 = bs(l=0, cls=(x86_imm_fix, m_arg), ival = 3)
2984 
2985 d0 = bs("000", fname='reg')
2986 d1 = bs("001", fname='reg')
2987 d2 = bs("010", fname='reg')
2988 d3 = bs("011", fname='reg')
2989 d4 = bs("100", fname='reg')
2990 d5 = bs("101", fname='reg')
2991 d6 = bs("110", fname='reg')
2992 d7 = bs("111", fname='reg')
2993 
2994 sd = bs(l=1, fname="sd")
2995 wd = bs(l=1, fname="wd")
2996 
2997 stk = bs(l=0, fname="stk")
2998 
2999 
3001  prio = default_prio
3002 
3003  def __init__(self, d=None):
3004  if d is None:
3005  d = {}
3006  self.d = d
3007 
3008  def get(self, opm, adm=None):
3009  return self.d[opm]
3010 
3012  def encode(self):
3013  return self.value != 0b11
3014 
3015  def decode(self, v):
3016  self.value = v
3017  return v != 0b11
3018 
3019 d_imm64 = bs(l=0, fname="imm64")
3020 
3021 d_eax = bs(l=0, cls=(bs_eax, ), fname='eax')
3022 d_edx = bs(l=0, cls=(bs_edx, ), fname='edx')
3023 d_st = bs(l=0, cls=(x86_reg_st, ), fname='st')
3024 d_imm = bs(l=0, cls=(bs_cond_imm,), fname="imm")
3025 d_imm64 = bs(l=0, cls=(bs_cond_imm64,), fname="imm")
3026 d_ax = bs(l=0, cls=(r_ax, ), fname='ax')
3027 d_dx = bs(l=0, cls=(r_dx, ), fname='dx')
3028 d_cl = bs(l=0, cls=(r_cl, ), fname='cl')
3029 
3030 d_cs = bs(l=0, cls=(bs_cs, ), fname='cs')
3031 d_ds = bs(l=0, cls=(bs_ds, ), fname='ds')
3032 d_es = bs(l=0, cls=(bs_es, ), fname='es')
3033 d_ss = bs(l=0, cls=(bs_ss, ), fname='ss')
3034 d_fs = bs(l=0, cls=(bs_fs, ), fname='fs')
3035 d_gs = bs(l=0, cls=(bs_gs, ), fname='gs')
3036 
3037 # Offset must be decoded in last position to have final instruction len
3038 rel_off = bs(l=0, cls=(bs_rel_off,), fname="off", order=-1)
3039 # Offset must be decoded in last position to have final instruction len
3040 rel_off08 = bs(l=8, cls=(bs_rel_off08,), fname="off", order=-1)
3041 moff = bs(l=0, cls=(bs_moff,), fname="off")
3042 msegoff = bs(l=16, cls=(bs_msegoff,), fname="mseg")
3043 movoff = bs(l=0, cls=(bs_movoff,), fname="off")
3044 mod = bs(l=2, fname="mod")
3045 mod_mem = bs(l=2, cls=(bs_mem,), fname="mod")
3046 
3047 rmreg = bs(l=3, cls=(x86_rm_reg, ), order =1, fname = "reg")
3048 reg = bs(l=3, cls=(x86_reg, ), order =1, fname = "reg")
3049 regnoarg = bs(l=3, default_val="000", order=1, fname="reg")
3050 segm = bs(l=3, cls=(x86_rm_segm, ), order =1, fname = "reg")
3051 crreg = bs(l=3, cls=(x86_rm_cr, ), order =1, fname = "reg")
3052 drreg = bs(l=3, cls=(x86_rm_dr, ), order =1, fname = "reg")
3053 
3054 
3055 mm_reg = bs(l=3, cls=(x86_rm_reg_mm, ), order =1, fname = "reg")
3056 xmm_reg = bs(l=3, cls=(x86_rm_reg_xmm, ), order =1, fname = "reg")
3057 
3058 
3059 fltreg = bs(l=3, cls=(x86_rm_flt, ), order =1, fname = "reg")
3060 
3061 rm = bs(l=3, fname="rm")
3062 
3063 rm_arg = bs(l=0, cls=(x86_rm_arg,), fname='rmarg')
3064 rm_arg_w8 = bs(l=0, cls=(x86_rm_w8,), fname='rmarg')
3065 rm_arg_sx = bs(l=0, cls=(x86_rm_sx,), fname='rmarg')
3066 rm_arg_sxd = bs(l=0, cls=(x86_rm_sxd,), fname='rmarg')
3067 rm_arg_sd = bs(l=0, cls=(x86_rm_sd,), fname='rmarg')
3068 rm_arg_wd = bs(l=0, cls=(x86_rm_wd,), fname='rmarg')
3069 rm_arg_m64 = bs(l=0, cls=(x86_rm_m64,), fname='rmarg')
3070 rm_arg_m80 = bs(l=0, cls=(x86_rm_m80,), fname='rmarg')
3071 rm_arg_m08 = bs(l=0, cls=(x86_rm_m08,), fname='rmarg')
3072 rm_arg_m16 = bs(l=0, cls=(x86_rm_m16,), fname='rmarg')
3073 
3074 rm_arg_mm = bs(l=0, cls=(x86_rm_mm,), fname='rmarg')
3075 rm_arg_mm_m64 = bs(l=0, cls=(x86_rm_mm_m64,), fname='rmarg')
3076 
3077 rm_arg_xmm = bs(l=0, cls=(x86_rm_xmm,), fname='rmarg')
3078 rm_arg_xmm_m32 = bs(l=0, cls=(x86_rm_xmm_m32,), fname='rmarg')
3079 rm_arg_xmm_m64 = bs(l=0, cls=(x86_rm_xmm_m64,), fname='rmarg')
3080 
3081 swapargs = bs_swapargs(l=1, fname="swap", mn_mod=range(1 << 1))
3082 
3083 
3084 cond_list = ["O", "NO", "B", "AE",
3085  "Z", "NZ", "BE", "A",
3086  "S", "NS", "PE", "NP",
3087  #"L", "NL", "NG", "G"]
3088  "L", "GE", "LE", "G"]
3089 cond = bs_mod_name(l=4, fname='cond', mn_mod=cond_list)
3090 
3091 
3092 def rmmod(r, rm_arg_x=rm_arg, modrm=mod):
3093  return [modrm, r, rm, sib_scale, sib_index, sib_base, disp, rm_arg_x]
3094 
3095 #
3096 # mode | reg | rm #
3097 #
3098 
3099 #
3100 # scale | index | base #
3101 #
3102 
3103 #
3104 # Prefix | REX prefix | Opcode | mod/rm | sib | displacement | immediate #
3105 #
3106 
3107 
3108 def addop(name, fields, args=None, alias=False):
3109  dct = {"fields": fields}
3110  dct["alias"] = alias
3111  if args is not None:
3112  dct['args'] = args
3113  type(name, (mn_x86,), dct)
3114 """
3115 class ia32_aaa(mn_x86):
3116  fields = [bs8(0x37)]
3117 """
3118 addop("aaa", [bs8(0x37)])
3119 addop("aas", [bs8(0x3F)])
3120 addop("aad", [bs8(0xd5), u08])
3121 addop("aam", [bs8(0xd4), u08])
3122 
3123 addop("adc", [bs("0001010"), w8, d_eax, d_imm])
3124 addop("adc", [bs("100000"), se, w8] + rmmod(d2, rm_arg_w8) + [d_imm])
3125 addop("adc", [bs("000100"), swapargs, w8] +
3126  rmmod(rmreg, rm_arg_w8), [rm_arg_w8, rmreg])
3127 
3128 addop("add", [bs("0000010"), w8, d_eax, d_imm])
3129 addop("add", [bs("100000"), se, w8] + rmmod(d0, rm_arg_w8) + [d_imm])
3130 addop("add", [bs("000000"), swapargs, w8] +
3131  rmmod(rmreg, rm_arg_w8), [rm_arg_w8, rmreg])
3132 
3133 addop("and", [bs("0010010"), w8, d_eax, d_imm])
3134 addop("and", [bs("100000"), se, w8] + rmmod(d4, rm_arg_w8) + [d_imm])
3135 addop("and", [bs("001000"), swapargs, w8] +
3136  rmmod(rmreg, rm_arg_w8), [rm_arg_w8, rmreg])
3137 
3138 addop("bsf", [bs8(0x0f), bs8(0xbc)] + rmmod(rmreg))
3139 addop("bsr", [bs8(0x0f), bs8(0xbd), mod,
3140  rmreg, rm, sib_scale, sib_index, sib_base, disp, rm_arg])
3141 
3142 addop("bswap", [bs8(0x0f), bs('11001'), reg])
3143 
3144 addop("bt", [bs8(0x0f), bs8(0xa3)] + rmmod(rmreg), [rm_arg, rmreg])
3145 addop("bt", [bs8(0x0f), bs8(0xba)] + rmmod(d4) + [u08])
3146 addop("btc", [bs8(0x0f), bs8(0xbb)] + rmmod(rmreg), [rm_arg, rmreg])
3147 addop("btc", [bs8(0x0f), bs8(0xba)] + rmmod(d7) + [u08])
3148 
3149 
3150 addop("btr", [bs8(0x0f), bs8(0xb3)] + rmmod(rmreg), [rm_arg, rmreg])
3151 addop("btr", [bs8(0x0f), bs8(0xba)] + rmmod(d6) + [u08])
3152 addop("bts", [bs8(0x0f), bs8(0xab)] + rmmod(rmreg), [rm_arg, rmreg])
3153 addop("bts", [bs8(0x0f), bs8(0xba)] + rmmod(d5) + [u08])
3154 
3155 addop("call", [bs8(0xe8), rel_off])
3156 addop("call", [bs8(0xff), stk] + rmmod(d2))
3157 addop("call", [bs8(0xff), stk] + rmmod(d3, modrm=mod_mem))
3158 addop("call", [bs8(0x9a), moff, msegoff])
3159 
3160 
3162 
3163  def decode(self, v):
3164  opmode = self.parent.v_opmode()
3165  return opmode == self.mode
3166 
3167 
3169 
3170  def decode(self, v):
3171  admode = self.parent.v_admode()
3172  return admode == self.mode
3173 
3174 
3176 
3177  def encode(self):
3178  if self.parent.mode == 64:
3179  return False
3180  return super(bs_op_mode_no64, self).encode()
3181 
3182  def decode(self, v):
3183  if self.parent.mode == 64:
3184  return False
3185  opmode = self.parent.v_opmode()
3186  return opmode == self.mode
3187 
3188 
3190  def encode(self):
3191  if self.parent.mode != 64:
3192  return False
3193  return super(bs_op_mode64, self).encode()
3194 
3195  def decode(self, v):
3196  if self.parent.mode != 64:
3197  return False
3198  return True
3199 
3201  def encode(self):
3202  if self.parent.mode == 64:
3203  return False
3204  return super(bs_op_modeno64, self).encode()
3205 
3206  def decode(self, v):
3207  if self.parent.mode == 64:
3208  return False
3209  return True
3210 
3211 
3212 
3213 bs_opmode16 = bs(l=0, cls=(bs_op_mode,), mode = 16, fname="fopmode")
3214 bs_opmode32 = bs(l=0, cls=(bs_op_mode,), mode = 32, fname="fopmode")
3215 bs_opmode64 = bs(l=0, cls=(bs_op_mode,), mode = 64, fname="fopmode")
3216 
3217 
3218 bs_admode16 = bs(l=0, cls=(bs_ad_mode,), mode = 16, fname="fadmode")
3219 bs_admode32 = bs(l=0, cls=(bs_ad_mode,), mode = 32, fname="fadmode")
3220 bs_admode64 = bs(l=0, cls=(bs_ad_mode,), mode = 64, fname="fadmode")
3221 
3222 bs_opmode16_no64 = bs(l=0, cls=(bs_op_mode_no64,), mode = 16, fname="fopmode")
3223 bs_opmode32_no64 = bs(l=0, cls=(bs_op_mode_no64,), mode = 32, fname="fopmode")
3224 
3225 bs_mode64 = bs(l=0, cls=(bs_op_mode64,))
3226 bs_modeno64 = bs(l=0, cls=(bs_op_modeno64,))
3227 
3228 addop("cbw", [bs8(0x98), bs_opmode16])
3229 addop("cwde", [bs8(0x98), bs_opmode32])
3230 addop("cdqe", [bs8(0x98), bs_opmode64])
3231 
3232 addop("clc", [bs8(0xf8)])
3233 addop("cld", [bs8(0xfc)])
3234 addop("cli", [bs8(0xfa)])
3235 addop("clts", [bs8(0x0f), bs8(0x06)])
3236 addop("cmc", [bs8(0xf5)])
3237 
3238 addop("cmov", [bs8(0x0f), bs('0100'), cond] + rmmod(rmreg))
3239 
3240 addop("cmp", [bs("0011110"), w8, d_eax, d_imm])
3241 addop("cmp", [bs("100000"), se, w8] + rmmod(d7, rm_arg_w8) + [d_imm])
3242 addop("cmp", [bs("001110"), swapargs, w8] +
3243  rmmod(rmreg, rm_arg_w8), [rm_arg_w8, rmreg])
3244 
3245 
3246 addop("cmpsb", [bs8(0xa6)])
3247 addop("cmpsw", [bs8(0xa7), bs_opmode16])
3248 addop("cmpsd", [bs8(0xa7), bs_opmode32])
3249 addop("cmpsq", [bs8(0xa7), bs_opmode64])
3250 
3251 addop("cmpxchg", [bs8(0x0f), bs('1011000'), w8]
3252  + rmmod(rmreg, rm_arg_w8), [rm_arg_w8, rmreg])
3253 # XXX TODO CMPXCHG8/16
3254 
3255 addop("comiss", [bs8(0x0f), bs8(0x2f), no_xmm_pref] +
3256  rmmod(xmm_reg, rm_arg_xmm_m32), [xmm_reg, rm_arg_xmm_m32])
3257 addop("comisd", [bs8(0x0f), bs8(0x2f), pref_66] +
3258  rmmod(xmm_reg, rm_arg_xmm_m64), [xmm_reg, rm_arg_xmm_m64])
3259 
3260 addop("cpuid", [bs8(0x0f), bs8(0xa2)])
3261 
3262 addop("cwd", [bs8(0x99), bs_opmode16])
3263 addop("cdq", [bs8(0x99), bs_opmode32])
3264 addop("cqo", [bs8(0x99), bs_opmode64])
3265 
3266 
3267 addop("daa", [bs8(0x27)])
3268 addop("das", [bs8(0x2f)])
3269 addop("dec", [bs('1111111'), w8] + rmmod(d1, rm_arg_w8))
3270 addop("dec", [bs('01001'), reg])
3271 addop("div", [bs('1111011'), w8] + rmmod(d6, rm_arg_w8))
3272 addop("enter", [bs8(0xc8), u16, u08])
3273 
3274 # float #####
3275 addop("fwait", [bs8(0x9b)])
3276 
3277 addop("f2xm1", [bs8(0xd9), bs8(0xf0)])
3278 addop("fabs", [bs8(0xd9), bs8(0xe1)])
3279 
3280 addop("fadd", [bs("11011"), sd, bs("00")] + rmmod(d0, rm_arg_sd))
3281 addop("fadd", [bs("11011"), swapargs, bs("00"),
3282  bs("11000"), d_st, fltreg], [d_st, fltreg])
3283 addop("faddp", [bs8(0xde), bs("11000"), fltreg, d_st])
3284 addop("fiadd", [bs("11011"), wd, bs("10")] + rmmod(d0, rm_arg_wd))
3285 
3286 addop("fbld", [bs8(0xdf)] + rmmod(d4, rm_arg_m80))
3287 addop("fbldp", [bs8(0xdf)] + rmmod(d6, rm_arg_m80))
3288 addop("fchs", [bs8(0xd9), bs8(0xe0)])
3289 # addop("fclex", [bs8(0x9b), bs8(0xdb), bs8(0xe2)])
3290 addop("fnclex", [bs8(0xdb), bs8(0xe2)])
3291 
3292 addop("fcmovb", [bs8(0xda), bs("11000"), d_st, fltreg])
3293 addop("fcmove", [bs8(0xda), bs("11001"), d_st, fltreg])
3294 addop("fcmovbe", [bs8(0xda), bs("11010"), d_st, fltreg])
3295 addop("fcmovu", [bs8(0xda), bs("11011"), d_st, fltreg])
3296 addop("fcmovnb", [bs8(0xdb), bs("11000"), d_st, fltreg])
3297 addop("fcmovne", [bs8(0xdb), bs("11001"), d_st, fltreg])
3298 addop("fcmovnbe", [bs8(0xdb), bs("11010"), d_st, fltreg])
3299 addop("fcmovnu", [bs8(0xdb), bs("11011"), d_st, fltreg])
3300 
3301 addop("fcom", [bs("11011"), sd, bs("00")] + rmmod(d2, rm_arg_sd))
3302 addop("fcom", [bs("11011"), swapargs, bs("00"),
3303  bs("11010"), d_st, fltreg], [d_st, fltreg])
3304 addop("fcomp", [bs("11011"), sd, bs("00")] + rmmod(d3, rm_arg_sd))
3305 addop("fcomp",
3306  [bs("11011"), swapargs, bs("00"), bs("11011"),
3307  d_st, fltreg], [d_st, fltreg])
3308 addop("fcompp", [bs8(0xde), bs8(0xd9)])
3309 
3310 addop("fcomi", [bs8(0xdb), bs("11110"), d_st, fltreg])
3311 addop("fcomip", [bs8(0xdf), bs("11110"), d_st, fltreg])
3312 addop("fucomi", [bs8(0xdb), bs("11101"), d_st, fltreg])
3313 addop("fucomip", [bs8(0xdf), bs("11101"), d_st, fltreg])
3314 
3315 addop("fcos", [bs8(0xd9), bs8(0xff)])
3316 addop("fdecstp", [bs8(0xd9), bs8(0xf6)])
3317 
3318 
3319 addop("fdiv", [bs("11011"), sd, bs("00")] + rmmod(d6, rm_arg_sd))
3320 addop("fdiv", [bs8(0xd8), bs("11110"), d_st, fltreg])
3321 addop("fdiv", [bs8(0xdc), bs("11111"), fltreg, d_st])
3322 addop("fdivp", [bs8(0xde), bs("11111"), fltreg, d_st])
3323 addop("fidiv", [bs("11011"), wd, bs("10")] + rmmod(d6, rm_arg_wd))
3324 
3325 addop("fdivr", [bs("11011"), sd, bs("00")] + rmmod(d7, rm_arg_sd))
3326 addop("fdivr", [bs8(0xd8), bs("11111"), d_st, fltreg])
3327 addop("fdivr", [bs8(0xdc), bs("11110"), fltreg, d_st])
3328 addop("fdivrp", [bs8(0xde), bs("11110"), fltreg, d_st])
3329 addop("fidivr", [bs("11011"), wd, bs("10")] + rmmod(d7, rm_arg_wd))
3330 
3331 addop("ffree", [bs8(0xdd), bs("11000"), fltreg])
3332 addop("ficom", [bs("11011"), wd, bs("10")] + rmmod(d2, rm_arg_wd))
3333 addop("ficomp", [bs("11011"), wd, bs("10")] + rmmod(d3, rm_arg_wd))
3334 addop("fild", [bs("11011"), wd, bs("11")] + rmmod(d0, rm_arg_wd))
3335 addop("fild", [bs8(0xdf)] + rmmod(d5, rm_arg_m64))
3336 
3337 addop("fincstp", [bs8(0xd9), bs8(0xf7)])
3338 
3339 # addop("finit", [bs8(0x9b), bs8(0xdb), bs8(0xe3)])
3340 addop("fninit", [bs8(0xdb), bs8(0xe3)])
3341 
3342 addop("fist", [bs("11011"), wd, bs("11")] + rmmod(d2, rm_arg_wd))
3343 addop("fistp", [bs("11011"), wd, bs("11")] + rmmod(d3, rm_arg_wd))
3344 addop("fistp", [bs8(0xdf)] + rmmod(d7, rm_arg_m64))
3345 
3346 addop("fisttp", [bs("11011"), wd, bs("11")] + rmmod(d1, rm_arg_wd))
3347 addop("fisttp", [bs8(0xdd)] + rmmod(d1, rm_arg_m64))
3348 
3349 addop("fld", [bs("11011"), sd, bs("01")] + rmmod(d0, rm_arg_sd))
3350 addop("fld", [bs8(0xdb)] + rmmod(d5, rm_arg_m80))
3351 addop("fld", [bs8(0xd9), bs("11000"), fltreg])
3352 
3353 addop("fld1", [bs8(0xd9), bs8(0xe8)])
3354 addop("fldl2t", [bs8(0xd9), bs8(0xe9)])
3355 addop("fldl2e", [bs8(0xd9), bs8(0xea)])
3356 addop("fldpi", [bs8(0xd9), bs8(0xeb)])
3357 addop("fldlg2", [bs8(0xd9), bs8(0xec)])
3358 addop("fldln2", [bs8(0xd9), bs8(0xed)])
3359 addop("fldz", [bs8(0xd9), bs8(0xee)])
3360 
3361 addop("fldcw", [bs8(0xd9)] + rmmod(d5, rm_arg_m16))
3362 addop("fldenv", [bs8(0xd9)] + rmmod(d4, rm_arg_m80)) # XXX TODO: m14?
3363 
3364 addop("fmul", [bs("11011"), sd, bs("00")] + rmmod(d1, rm_arg_sd))
3365 addop("fmul", [bs("11011"), swapargs, bs("00"),
3366  bs("11001"), d_st, fltreg], [d_st, fltreg])
3367 addop("fmulp", [bs8(0xde), bs("11001"), fltreg, d_st])
3368 addop("fimul", [bs("11011"), wd, bs("10")] + rmmod(d1, rm_arg_wd))
3369 
3370 addop("fnop", [bs8(0xd9), bs8(0xd0)])
3371 addop("fpatan", [bs8(0xd9), bs8(0xf3)])
3372 addop("fprem", [bs8(0xd9), bs8(0xf8)])
3373 addop("fprem1", [bs8(0xd9), bs8(0xf5)])
3374 addop("fptan", [bs8(0xd9), bs8(0xf2)])
3375 addop("frndint", [bs8(0xd9), bs8(0xfc)])
3376 addop("frstor", [bs8(0xdd)] + rmmod(d4, rm_arg_m80)) # XXX TODO: m94 ?
3377 # addop("fsave", [bs8(0x9b), bs8(0xdd)] + rmmod(d6, rm_arg_m80)) # XXX
3378 # TODO: m94 ?
3379 addop("fnsave", [bs8(0xdd)] + rmmod(d6, rm_arg_m80)) # XXX TODO: m94 ?
3380 
3381 addop("fscale", [bs8(0xd9), bs8(0xfd)])
3382 addop("fsin", [bs8(0xd9), bs8(0xfe)])
3383 addop("fsincos", [bs8(0xd9), bs8(0xfb)])
3384 addop("fsqrt", [bs8(0xd9), bs8(0xfa)])
3385 
3386 addop("fst", [bs("11011"), sd, bs("01")] + rmmod(d2, rm_arg_sd))
3387 addop("fst", [bs8(0xdd), bs("11010"), fltreg])
3388 addop("fstp", [bs("11011"), sd, bs("01")] + rmmod(d3, rm_arg_sd))
3389 addop("fstp", [bs8(0xdb)] + rmmod(d7, rm_arg_m80))
3390 addop("fstp", [bs8(0xdd), bs("11011"), fltreg])
3391 
3392 # addop("fstcw", [bs8(0x9b), bs8(0xd9)] + rmmod(d7, rm_arg_m16))
3393 addop("fnstcw", [bs8(0xd9)] + rmmod(d7, rm_arg_m16))
3394 # addop("fstenv", [bs8(0x9b), bs8(0xd9)] + rmmod(d6, rm_arg_m80)) # XXX
3395 # TODO: m14?
3396 addop("fnstenv", [bs8(0xd9)] + rmmod(d6, rm_arg_m80)) # XXX TODO: m14?
3397 # addop("fstsw", [bs8(0x9b), bs8(0xdd)] + rmmod(d7, rm_arg_m16))
3398 addop("fnstsw", [bs8(0xdd)] + rmmod(d7, rm_arg_m16))
3399 # addop("fstsw", [bs8(0x9b), bs8(0xdf), bs8(0xe0), d_ax])
3400 addop("fnstsw", [bs8(0xdf), bs8(0xe0), d_ax])
3401 
3402 addop("fsub", [bs("11011"), sd, bs("00")] + rmmod(d4, rm_arg_sd))
3403 addop("fsub", [bs8(0xd8), bs("11100"), d_st, fltreg])
3404 addop("fsub", [bs8(0xdc), bs("11101"), fltreg, d_st])
3405 addop("fsubp", [bs8(0xde), bs("11101"), fltreg, d_st])
3406 addop("fisub", [bs("11011"), wd, bs("10")] + rmmod(d4, rm_arg_wd))
3407 
3408 addop("fsubr", [bs("11011"), sd, bs("00")] + rmmod(d5, rm_arg_sd))
3409 addop("fsubr", [bs8(0xd8), bs("11101"), d_st, fltreg])
3410 addop("fsubr", [bs8(0xdc), bs("11100"), fltreg, d_st])
3411 addop("fsubrp", [bs8(0xde), bs("11100"), fltreg, d_st])
3412 addop("fisubr", [bs("11011"), wd, bs("10")] + rmmod(d5, rm_arg_wd))
3413 addop("ftst", [bs8(0xd9), bs8(0xe4)])
3414 
3415 
3416 addop("fucom", [bs8(0xdd), bs("11100"), fltreg])
3417 addop("fucomp", [bs8(0xdd), bs("11101"), fltreg])
3418 addop("fucompp", [bs8(0xda), bs8(0xe9)])
3419 
3420 addop("fxam", [bs8(0xd9), bs8(0xe5)])
3421 addop("fxch", [bs8(0xd9), bs("11001"), fltreg])
3422 addop("fxrstor", [bs8(0x0f), bs8(0xae)]
3423  + rmmod(d1, rm_arg_m80)) # XXX TODO m512
3424 addop("fxsave", [bs8(0x0f), bs8(0xae)]
3425  + rmmod(d0, rm_arg_m80)) # XXX TODO m512
3426 addop("stmxcsr", [bs8(0x0f), bs8(0xae)] + rmmod(d3))
3427 addop("ldmxcsr", [bs8(0x0f), bs8(0xae)] + rmmod(d2))
3428 
3429 addop("fxtract", [bs8(0xd9), bs8(0xf4)])
3430 addop("fyl2x", [bs8(0xd9), bs8(0xf1)])
3431 addop("fyl2xp1", [bs8(0xd9), bs8(0xf9)])
3432 
3433 addop("hlt", [bs8(0xf4)])
3434 addop("icebp", [bs8(0xf1)])
3435 
3436 addop("idiv", [bs('1111011'), w8] + rmmod(d7, rm_arg_w8))
3437 
3438 addop("imul", [bs('1111011'), w8] + rmmod(d5, rm_arg_w8))
3439 addop("imul", [bs8(0x0f), bs8(0xaf)] + rmmod(rmreg))
3440 
3441 addop("imul", [bs("011010"), se, bs('1')] + rmmod(rmreg) + [d_imm])
3442 
3443 addop("in", [bs("1110010"), w8, d_eax, u08])
3444 addop("in", [bs("1110110"), w8, d_eax, d_edx])
3445 
3446 addop("inc", [bs('1111111'), w8] + rmmod(d0, rm_arg_w8))
3447 addop("inc", [bs('01000'), reg])
3448 
3449 addop("insb", [bs8(0x6c)])
3450 addop("insw", [bs8(0x6d), bs_opmode16])
3451 addop("insd", [bs8(0x6d), bs_opmode32])
3452 addop("insd", [bs8(0x6d), bs_opmode64])
3453 
3454 addop("int", [bs8(0xcc), u08_3])
3455 addop("int", [bs8(0xcd), u08])
3456 addop("into", [bs8(0xce)])
3457 addop("invd", [bs8(0x0f), bs8(0x08)])
3458 addop("invlpg", [bs8(0x0f), bs8(0x01)] + rmmod(d7))
3459 
3460 addop("iret", [bs8(0xcf), bs_opmode16])
3461 addop("iretd", [bs8(0xcf), bs_opmode32])
3462 addop("iretq", [bs8(0xcf), bs_opmode64])
3463 
3464 addop("j", [bs('0111'), cond, rel_off08])
3465 
3466 addop("jcxz", [bs8(0xe3), rel_off08, bs_admode16])
3467 addop("jecxz", [bs8(0xe3), rel_off08, bs_admode32])
3468 addop("jrcxz", [bs8(0xe3), rel_off08, bs_admode64])
3469 
3470 addop("j", [bs8(0x0f), bs('1000'), cond, rel_off])
3471 addop("jmp", [bs8(0xeb), rel_off08])
3472 addop("jmp", [bs8(0xe9), rel_off])
3473 # TODO XXX replace stk force64?
3474 addop("jmp", [bs8(0xff), stk] + rmmod(d4))
3475 addop("jmpf", [bs8(0xea), moff, msegoff])
3476 
3477 addop("jmpf", [bs8(0xff)] + rmmod(d5))
3478 
3479 addop("lahf", [bs8(0x9f)])
3480 addop("lar", [bs8(0x0f), bs8(0x02)] + rmmod(rmreg))
3481 
3482 addop("lea", [bs8(0x8d)] + rmmod(rmreg))
3483 addop("les", [bs8(0xc4)] + rmmod(rmreg))
3484 addop("lds", [bs8(0xc5)] + rmmod(rmreg))
3485 addop("lss", [bs8(0x0f), bs8(0xb2)] + rmmod(rmreg))
3486 addop("lfs", [bs8(0x0f), bs8(0xb4)] + rmmod(rmreg))
3487 addop("lgs", [bs8(0x0f), bs8(0xb5)] + rmmod(rmreg))
3488 
3489 addop("lgdt", [bs8(0x0f), bs8(0x01)] + rmmod(d2, modrm=mod_mem))
3490 addop("lidt", [bs8(0x0f), bs8(0x01)] + rmmod(d3, modrm=mod_mem))
3491 
3492 
3493 addop("leave", [bs8(0xc9), stk])
3494 
3495 addop("lodsb", [bs8(0xac)])
3496 addop("lodsw", [bs8(0xad), bs_opmode16])
3497 addop("lodsd", [bs8(0xad), bs_opmode32])
3498 addop("lodsq", [bs8(0xad), bs_opmode64])
3499 
3500 addop("loop", [bs8(0xe2), rel_off08])
3501 addop("loope", [bs8(0xe1), rel_off08])
3502 addop("loopne", [bs8(0xe0), rel_off08])
3503 addop("lsl", [bs8(0x0f), bs8(0x03)] + rmmod(rmreg))
3504 addop("monitor", [bs8(0x0f), bs8(0x01), bs8(0xc8)])
3505 
3506 addop("mov", [bs("100010"), swapargs, w8] +
3507  rmmod(rmreg, rm_arg_w8), [rm_arg_w8, rmreg])
3508 addop("mov", [bs("100011"), swapargs, bs('0')] + rmmod(segm), [rm_arg, segm])
3509 addop("mov", [bs("101000"), swapargs, w8, d_eax, movoff], [d_eax, movoff])
3510 addop("mov", [bs("1011"), w8, reg, d_imm64])
3511 addop("mov", [bs("1100011"), w8] + rmmod(d0, rm_arg_w8) + [d_imm])
3512 addop("mov", [bs8(0x0f), bs("001000"), swapargs, bs('0')]
3513  + rmmod(crreg), [rm_arg, crreg])
3514 addop("mov", [bs8(0x0f), bs("001000"), swapargs, bs('1')]
3515  + rmmod(drreg), [rm_arg, drreg])
3516 addop("movsb", [bs8(0xa4)])
3517 addop("movsw", [bs8(0xa5), bs_opmode16])
3518 addop("movsd", [bs8(0xa5), bs_opmode32])
3519 addop("movsq", [bs8(0xa5), bs_opmode64])
3520 
3521 addop("movsx", [bs8(0x0f), bs("1011111"), w8, sx] + rmmod(rmreg, rm_arg_sx))
3522 addop("movsxd", [bs8(0x63), sxd, bs_mode64] + rmmod(rmreg, rm_arg_sxd))
3523 
3524 addop("movups",
3525  [bs8(0x0f), bs8(0x10), no_xmm_pref] + rmmod(xmm_reg, rm_arg_xmm))
3526 addop("movsd", [bs8(0x0f), bs("0001000"), swapargs, pref_f2]
3527  + rmmod(xmm_reg, rm_arg_xmm_m64), [xmm_reg, rm_arg_xmm_m64])
3528 addop("movss", [bs8(0x0f), bs("0001000"), swapargs, pref_f3] +
3529  rmmod(xmm_reg, rm_arg_xmm_m32), [xmm_reg, rm_arg_xmm_m32])
3530 addop("movupd", [bs8(0x0f), bs8(0x10), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3531 
3532 
3533 addop("movd", [bs8(0x0f), bs('011'), swapargs, bs('1110'), no_xmm_pref] +
3534  rmmod(mm_reg, rm_arg), [mm_reg, rm_arg])
3535 addop("movd", [bs8(0x0f), bs('011'), swapargs, bs('1110'), pref_66, bs_opmode32] +
3536  rmmod(xmm_reg, rm_arg), [xmm_reg, rm_arg])
3537 addop("movq", [bs8(0x0f), bs('011'), swapargs, bs('1110'), pref_66, bs_opmode64] +
3538  rmmod(xmm_reg, rm_arg), [xmm_reg, rm_arg])
3539 
3540 addop("movq", [bs8(0x0f), bs('011'), swapargs, bs('1111'), no_xmm_pref] +
3541  rmmod(mm_reg, rm_arg_mm_m64), [mm_reg, rm_arg_mm_m64])
3542 
3543 addop("movq", [bs8(0x0f), bs8(0x7e), pref_f3] +
3544  rmmod(xmm_reg, rm_arg_xmm_m64), [xmm_reg, rm_arg_xmm_m64])
3545 addop("movq", [bs8(0x0f), bs8(0xd6), pref_66] +
3546  rmmod(xmm_reg, rm_arg_xmm_m64), [rm_arg_xmm_m64, xmm_reg])
3547 
3548 
3549 
3550 addop("addss", [bs8(0x0f), bs8(0x58), pref_f3] + rmmod(xmm_reg, rm_arg_xmm_m32))
3551 addop("addsd", [bs8(0x0f), bs8(0x58), pref_f2] + rmmod(xmm_reg, rm_arg_xmm_m64))
3552 
3553 addop("subss", [bs8(0x0f), bs8(0x5c), pref_f3] + rmmod(xmm_reg, rm_arg_xmm_m32))
3554 addop("subsd", [bs8(0x0f), bs8(0x5c), pref_f2] + rmmod(xmm_reg, rm_arg_xmm_m64))
3555 
3556 addop("mulss", [bs8(0x0f), bs8(0x59), pref_f3] + rmmod(xmm_reg, rm_arg_xmm_m32))
3557 addop("mulsd", [bs8(0x0f), bs8(0x59), pref_f2] + rmmod(xmm_reg, rm_arg_xmm_m64))
3558 
3559 addop("divss", [bs8(0x0f), bs8(0x5e), pref_f3] + rmmod(xmm_reg, rm_arg_xmm_m32))
3560 addop("divsd", [bs8(0x0f), bs8(0x5e), pref_f2] + rmmod(xmm_reg, rm_arg_xmm_m64))
3561 
3562 
3563 addop("pminsw", [bs8(0x0f), bs8(0xea), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm))
3564 addop("pminsw", [bs8(0x0f), bs8(0xea), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3565 
3566 addop("ucomiss", [bs8(0x0f), bs8(0x2e), no_xmm_pref] + rmmod(xmm_reg, rm_arg_xmm_m32))
3567 addop("ucomisd", [bs8(0x0f), bs8(0x2e), pref_66] + rmmod(xmm_reg, rm_arg_xmm_m64))
3568 
3569 addop("maxsd", [bs8(0x0f), bs8(0x5f), pref_f2] + rmmod(xmm_reg, rm_arg_xmm_m64))
3570 addop("maxss", [bs8(0x0f), bs8(0x5f), pref_f3] + rmmod(xmm_reg, rm_arg_xmm_m32))
3571 
3572 
3573 
3574 addop("movzx", [bs8(0x0f), bs("1011011"), w8, sx] + rmmod(rmreg, rm_arg_sx))
3575 addop("mul", [bs('1111011'), w8] + rmmod(d4, rm_arg_w8))
3576 
3577 addop("neg", [bs('1111011'), w8] + rmmod(d3, rm_arg_w8))
3578 addop("nop", [bs8(0x0f), bs8(0x1f)] + rmmod(d0, rm_arg)) # XXX TODO m512
3579 addop("not", [bs('1111011'), w8] + rmmod(d2, rm_arg_w8))
3580 addop("or", [bs("0000110"), w8, d_eax, d_imm])
3581 addop("or", [bs("100000"), se, w8] + rmmod(d1, rm_arg_w8) + [d_imm])
3582 addop("or", [bs("000010"), swapargs, w8] +
3583  rmmod(rmreg, rm_arg_w8), [rm_arg_w8, rmreg])
3584 addop("out", [bs("1110011"), w8, u08, d_eax])
3585 addop("out", [bs("1110111"), w8, d_edx, d_eax])
3586 
3587 addop("outsb", [bs8(0x6e)])
3588 addop("outsw", [bs8(0x6f), bs_opmode16])
3589 addop("outsd", [bs8(0x6f), bs_opmode32])
3590 addop("outsd", [bs8(0x6f), bs_opmode64])
3591 
3592 
3593 # addop("pause", [bs8(0xf3), bs8(0x90)])
3594 
3595 addop("popw", [bs8(0x8f), stk, bs_opmode16] + rmmod(d0))
3596 addop("popw", [bs("01011"), stk, reg, bs_opmode16])
3597 addop("popw", [bs8(0x1f), stk, d_ds, bs_opmode16])
3598 addop("popw", [bs8(0x07), stk, d_es, bs_opmode16])
3599 addop("popw", [bs8(0x17), stk, d_ss, bs_opmode16])
3600 addop("popw", [bs8(0x0f), stk, bs8(0xa1), d_fs, bs_opmode16])
3601 addop("popw", [bs8(0x0f), stk, bs8(0xa9), d_gs, bs_opmode16])
3602 
3603 addop("pop", [bs8(0x8f), stk, bs_opmode32] + rmmod(d0))
3604 addop("pop", [bs("01011"), stk, reg, bs_opmode32])
3605 addop("pop", [bs8(0x1f), stk, d_ds, bs_opmode32])
3606 addop("pop", [bs8(0x07), stk, d_es, bs_opmode32])
3607 addop("pop", [bs8(0x17), stk, d_ss, bs_opmode32])
3608 addop("pop", [bs8(0x0f), stk, bs8(0xa1), d_fs, bs_opmode32])
3609 addop("pop", [bs8(0x0f), stk, bs8(0xa9), d_gs, bs_opmode32])
3610 
3611 addop("pop", [bs8(0x8f), stk, bs_opmode64] + rmmod(d0))
3612 addop("pop", [bs("01011"), stk, reg, bs_opmode64])
3613 addop("pop", [bs8(0x1f), stk, d_ds, bs_opmode64])
3614 addop("pop", [bs8(0x07), stk, d_es, bs_opmode64])
3615 addop("pop", [bs8(0x17), stk, d_ss, bs_opmode64])
3616 addop("pop", [bs8(0x0f), stk, bs8(0xa1), d_fs, bs_opmode64])
3617 addop("pop", [bs8(0x0f), stk, bs8(0xa9), d_gs, bs_opmode64])
3618 
3619 
3620 addop("popa", [bs8(0x61), stk, bs_opmode16])
3621 addop("popad", [bs8(0x61), stk, bs_opmode32])
3622 
3623 addop("popfw", [bs8(0x9d), stk, bs_opmode16])
3624 addop("popfd", [bs8(0x9d), stk, bs_opmode32])
3625 addop("popfq", [bs8(0x9d), stk, bs_opmode64])
3626 
3627 addop("prefetch0", [bs8(0x0f), bs8(0x18)] + rmmod(d1, rm_arg_m08))
3628 addop("prefetch1", [bs8(0x0f), bs8(0x18)] + rmmod(d2, rm_arg_m08))
3629 addop("prefetch2", [bs8(0x0f), bs8(0x18)] + rmmod(d3, rm_arg_m08))
3630 addop("prefetchnta", [bs8(0x0f), bs8(0x18)] + rmmod(d0, rm_arg_m08))
3631 
3632 addop("pushw", [bs8(0xff), stk, bs_opmode16] + rmmod(d6))
3633 addop("pushw", [bs("01010"), stk, reg, bs_opmode16])
3634 addop("pushw", [bs8(0x6a), s08, stk, bs_opmode16])
3635 addop("pushw", [bs8(0x68), d_imm, stk, bs_opmode16])
3636 addop("pushw", [bs8(0x0e), stk, d_cs, bs_opmode16])
3637 addop("pushw", [bs8(0x16), stk, d_ss, bs_opmode16])
3638 addop("pushw", [bs8(0x1e), stk, d_ds, bs_opmode16])
3639 addop("pushw", [bs8(0x06), stk, d_es, bs_opmode16])
3640 addop("pushw", [bs8(0x0f), stk, bs8(0xa0), d_fs, bs_opmode16])
3641 addop("pushw", [bs8(0x0f), stk, bs8(0xa8), d_gs, bs_opmode16])
3642 
3643 addop("push", [bs8(0xff), stk, bs_opmode32] + rmmod(d6))
3644 addop("push", [bs("01010"), stk, reg, bs_opmode32])
3645 addop("push", [bs8(0x6a), s08, stk, bs_opmode32])
3646 addop("push", [bs8(0x68), d_imm, stk, bs_opmode32])
3647 addop("push", [bs8(0x0e), stk, d_cs, bs_opmode32])
3648 addop("push", [bs8(0x16), stk, d_ss, bs_opmode32])
3649 addop("push", [bs8(0x1e), stk, d_ds, bs_opmode32])
3650 addop("push", [bs8(0x06), stk, d_es, bs_opmode32])
3651 addop("push", [bs8(0x0f), stk, bs8(0xa0), d_fs, bs_opmode32])
3652 addop("push", [bs8(0x0f), stk, bs8(0xa8), d_gs, bs_opmode32])
3653 
3654 addop("push", [bs8(0xff), stk, bs_opmode64] + rmmod(d6))
3655 addop("push", [bs("01010"), stk, reg, bs_opmode64])
3656 addop("push", [bs8(0x6a), s08, stk, bs_opmode64])
3657 addop("push", [bs8(0x68), d_imm, stk, bs_opmode64])
3658 addop("push", [bs8(0x0e), stk, d_cs, bs_opmode64])
3659 addop("push", [bs8(0x16), stk, d_ss, bs_opmode64])
3660 addop("push", [bs8(0x1e), stk, d_ds, bs_opmode64])
3661 addop("push", [bs8(0x06), stk, d_es, bs_opmode64])
3662 addop("push", [bs8(0x0f), stk, bs8(0xa0), d_fs, bs_opmode64])
3663 addop("push", [bs8(0x0f), stk, bs8(0xa8), d_gs, bs_opmode64])
3664 
3665 addop("pusha", [bs8(0x60), stk, bs_opmode16_no64])
3666 addop("pushad", [bs8(0x60), stk, bs_opmode32_no64])
3667 
3668 
3669 addop("pushfw", [bs8(0x9c), stk, bs_opmode16])
3670 addop("pushfd", [bs8(0x9c), stk, bs_opmode32])
3671 addop("pushfq", [bs8(0x9c), stk, bs_opmode64])
3672 
3673 addop("rcl", [bs('110100'), d_cl1, w8] +
3674  rmmod(d2, rm_arg_w8), [rm_arg_w8, d_cl1])
3675 addop("rcl", [bs('1100000'), w8] + rmmod(d2, rm_arg_w8) + [u08])
3676 addop("rcr", [bs('110100'), d_cl1, w8] +
3677  rmmod(d3, rm_arg_w8), [rm_arg_w8, d_cl1])
3678 addop("rcr", [bs('1100000'), w8] + rmmod(d3, rm_arg_w8) + [u08])
3679 addop("rol", [bs('110100'), d_cl1, w8]
3680  + rmmod(d0, rm_arg_w8), [rm_arg_w8, d_cl1])
3681 addop("rol", [bs('1100000'), w8] + rmmod(d0, rm_arg_w8) + [u08])
3682 addop("ror", [bs('110100'), d_cl1, w8]
3683  + rmmod(d1, rm_arg_w8), [rm_arg_w8, d_cl1])
3684 addop("ror", [bs('1100000'), w8] + rmmod(d1, rm_arg_w8) + [u08])
3685 
3686 addop("rdmsr", [bs8(0x0f), bs8(0x32)])
3687 addop("rdpmc", [bs8(0x0f), bs8(0x33)])
3688 addop("rdtsc", [bs8(0x0f), bs8(0x31)])
3689 addop("ret", [bs8(0xc3), stk])
3690 addop("ret", [bs8(0xc2), stk, u16])
3691 addop("retf", [bs8(0xcb), stk])
3692 addop("retf", [bs8(0xca), stk, u16])
3693 
3694 addop("rsm", [bs8(0x0f), bs8(0xaa)])
3695 addop("sahf", [bs8(0x9e)])
3696 
3697 # XXX tipo in doc: /4 instead of /6
3698 addop("sal", [bs('110100'), d_cl1, w8] +
3699  rmmod(d6, rm_arg_w8), [rm_arg_w8, d_cl1])
3700 addop("sal", [bs('1100000'), w8] + rmmod(d6, rm_arg_w8) + [u08])
3701 addop("sar", [bs('110100'), d_cl1, w8] +
3702  rmmod(d7, rm_arg_w8), [rm_arg_w8, d_cl1])
3703 addop("sar", [bs('1100000'), w8] + rmmod(d7, rm_arg_w8) + [u08])
3704 
3705 addop("scasb", [bs8(0xae)])
3706 addop("scasw", [bs8(0xaf), bs_opmode16])
3707 addop("scasd", [bs8(0xaf), bs_opmode32])
3708 addop("scasq", [bs8(0xaf), bs_opmode64])
3709 
3710 addop("shl", [bs('110100'), d_cl1, w8]
3711  + rmmod(d4, rm_arg_w8), [rm_arg_w8, d_cl1])
3712 addop("shl", [bs('1100000'), w8] + rmmod(d4, rm_arg_w8) + [u08])
3713 addop("shr", [bs('110100'), d_cl1, w8]
3714  + rmmod(d5, rm_arg_w8), [rm_arg_w8, d_cl1])
3715 addop("shr", [bs('1100000'), w8] + rmmod(d5, rm_arg_w8) + [u08])
3716 
3717 addop("sbb", [bs("0001110"), w8, d_eax, d_imm])
3718 addop("sbb", [bs("100000"), se, w8] + rmmod(d3, rm_arg_w8) + [d_imm])
3719 addop("sbb", [bs("000110"), swapargs, w8] +
3720  rmmod(rmreg, rm_arg_w8), [rm_arg_w8, rmreg])
3721 
3722 addop("set", [bs8(0x0f), bs('1001'), cond] + rmmod(regnoarg, rm_arg_m08))
3723 addop("sgdt", [bs8(0x0f), bs8(0x01)] + rmmod(d0, modrm=mod_mem))
3724 addop("shld", [bs8(0x0f), bs8(0xa4)] +
3725  rmmod(rmreg) + [u08], [rm_arg, rmreg, u08])
3726 addop("shld", [bs8(0x0f), bs8(0xa5)] +
3727  rmmod(rmreg) + [d_cl], [rm_arg, rmreg, d_cl])
3728 addop("shrd", [bs8(0x0f), bs8(0xac)] +
3729  rmmod(rmreg) + [u08], [rm_arg, rmreg, u08])
3730 addop("shrd", [bs8(0x0f), bs8(0xad)] +
3731  rmmod(rmreg) + [d_cl], [rm_arg, rmreg, d_cl])
3732 addop("sidt", [bs8(0x0f), bs8(0x01)] + rmmod(d1, modrm=mod_mem))
3733 addop("sldt", [bs8(0x0f), bs8(0x00)] + rmmod(d0, modrm=mod_mem))
3734 addop("smsw", [bs8(0x0f), bs8(0x01)] + rmmod(d4))
3735 addop("stc", [bs8(0xf9)])
3736 addop("std", [bs8(0xfd)])
3737 addop("sti", [bs8(0xfb)])
3738 addop("stosb", [bs8(0xaa)])
3739 addop("stosw", [bs8(0xab), bs_opmode16])
3740 addop("stosd", [bs8(0xab), bs_opmode32])
3741 addop("stosq", [bs8(0xab), bs_opmode64])
3742 
3743 addop("str", [bs8(0x0f), bs8(0x00)] + rmmod(d1))
3744 
3745 addop("sub", [bs("0010110"), w8, d_eax, d_imm])
3746 addop("sub", [bs("100000"), se, w8] + rmmod(d5, rm_arg_w8) + [d_imm])
3747 addop("sub", [bs("001010"), swapargs, w8] +
3748  rmmod(rmreg, rm_arg_w8), [rm_arg_w8, rmreg])
3749 
3750 addop("syscall", [bs8(0x0f), bs8(0x05)])
3751 addop("sysenter", [bs8(0x0f), bs8(0x34)])
3752 addop("sysexit", [bs8(0x0f), bs8(0x35)])
3753 addop("sysret", [bs8(0x0f), bs8(0x07)])
3754 addop("test", [bs("1010100"), w8, d_eax, d_imm])
3755 addop("test", [bs("1111011"), w8] + rmmod(d0, rm_arg_w8) + [d_imm])
3756 addop("test", [bs("1000010"), w8] +
3757  rmmod(rmreg, rm_arg_w8), [rm_arg_w8, rmreg])
3758 addop("ud2", [bs8(0x0f), bs8(0x0b)])
3759 addop("verr", [bs8(0x0f), bs8(0x00)] + rmmod(d4))
3760 addop("verw", [bs8(0x0f), bs8(0x00)] + rmmod(d5))
3761 addop("wbinvd", [bs8(0x0f), bs8(0x09)])
3762 addop("wrmsr", [bs8(0x0f), bs8(0x30)])
3763 addop("xadd", [bs8(0x0f), bs("1100000"), w8]
3764  + rmmod(rmreg, rm_arg_w8), [rm_arg_w8, rmreg])
3765 
3766 addop("nop", [bs8(0x90)], alias=True)
3767 
3768 addop("xchg", [bs('10010'), d_eax, reg])
3769 addop("xchg", [bs('1000011'), w8] +
3770  rmmod(rmreg, rm_arg_w8), [rm_arg_w8, rmreg])
3771 addop("xlat", [bs8(0xd7)])
3772 
3773 
3774 addop("xor", [bs("0011010"), w8, d_eax, d_imm])
3775 addop("xor", [bs("100000"), se, w8] + rmmod(d6, rm_arg_w8) + [d_imm])
3776 addop("xor", [bs("001100"), swapargs, w8] +
3777  rmmod(rmreg, rm_arg_w8), [rm_arg_w8, rmreg])
3778 
3779 
3780 addop("xgetbv", [bs8(0x0f), bs8(0x01), bs8(0xd0)])
3781 
3782 
3783 
3784 #### MMX/SSE/AVX operations
3785 ####┬áCategories are the same than here: https://software.intel.com/sites/landingpage/IntrinsicsGuide/
3786 ####
3787 
3788 ### Arithmetic (integers)
3789 ###
3790 
3791 ## Move
3792 # SSE
3793 addop("movapd", [bs8(0x0f), bs("0010100"), swapargs]
3794  + rmmod(xmm_reg, rm_arg_xmm) + [bs_opmode16], [xmm_reg, rm_arg_xmm])
3795 addop("movaps", [bs8(0x0f), bs("0010100"), swapargs]
3796  + rmmod(xmm_reg, rm_arg_xmm) + [bs_opmode32], [xmm_reg, rm_arg_xmm])
3797 addop("movaps", [bs8(0x0f), bs("0010100"), swapargs]
3798  + rmmod(xmm_reg, rm_arg_xmm) + [bs_opmode64], [xmm_reg, rm_arg_xmm])
3799 addop("movdqu", [bs8(0x0f), bs("011"), swapargs, bs("1111"), pref_f3]
3800  + rmmod(xmm_reg, rm_arg_xmm), [xmm_reg, rm_arg_xmm])
3801 addop("movdqa", [bs8(0x0f), bs("011"), swapargs, bs("1111"), pref_66]
3802  + rmmod(xmm_reg, rm_arg_xmm), [xmm_reg, rm_arg_xmm])
3803 
3804 
3805 
3806 ## Additions
3807 # SSE
3808 addop("paddb", [bs8(0x0f), bs8(0xfc), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3809 addop("paddw", [bs8(0x0f), bs8(0xfd), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3810 addop("paddd", [bs8(0x0f), bs8(0xfe), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3811 addop("paddq", [bs8(0x0f), bs8(0xd4), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3812 
3813 addop("paddb", [bs8(0x0f), bs8(0xfc), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm))
3814 addop("paddw", [bs8(0x0f), bs8(0xfd), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm))
3815 addop("paddd", [bs8(0x0f), bs8(0xfe), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm))
3816 addop("paddq", [bs8(0x0f), bs8(0xd4), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm))
3817 
3818 ## Substractions
3819 # SSE
3820 addop("psubb", [bs8(0x0f), bs8(0xf8), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3821 addop("psubw", [bs8(0x0f), bs8(0xf9), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3822 addop("psubd", [bs8(0x0f), bs8(0xfa), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3823 addop("psubq", [bs8(0x0f), bs8(0xfb), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3824 
3825 addop("psubb", [bs8(0x0f), bs8(0xf8), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm))
3826 addop("psubw", [bs8(0x0f), bs8(0xf9), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm))
3827 addop("psubd", [bs8(0x0f), bs8(0xfa), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm))
3828 addop("psubq", [bs8(0x0f), bs8(0xfb), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm))
3829 
3830 ### Arithmetic (floating-point)
3831 ###
3832 
3833 ## Additions
3834 # SSE
3835 addop("addps", [bs8(0x0f), bs8(0x58), no_xmm_pref] + rmmod(xmm_reg, rm_arg_xmm))
3836 addop("addpd", [bs8(0x0f), bs8(0x58), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3837 
3838 ## Substractions
3839 # SSE
3840 addop("subps", [bs8(0x0f), bs8(0x5c), no_xmm_pref] + rmmod(xmm_reg, rm_arg_xmm))
3841 addop("subpd", [bs8(0x0f), bs8(0x5c), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3842 
3843 ## Multiplications
3844 # SSE
3845 addop("mulps", [bs8(0x0f), bs8(0x59), no_xmm_pref] + rmmod(xmm_reg, rm_arg_xmm))
3846 addop("mulpd", [bs8(0x0f), bs8(0x59), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3847 
3848 ## Divisions
3849 # SSE
3850 addop("divps", [bs8(0x0f), bs8(0x5e), no_xmm_pref] + rmmod(xmm_reg, rm_arg_xmm))
3851 addop("divpd", [bs8(0x0f), bs8(0x5e), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3852 
3853 ### Logical (floating-point)
3854 ###
3855 
3856 ## XOR
3857 addop("xorps", [bs8(0x0f), bs8(0x57), no_xmm_pref] + rmmod(xmm_reg, rm_arg_xmm))
3858 addop("xorpd", [bs8(0x0f), bs8(0x57), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3859 
3860 ## AND
3861 addop("andps", [bs8(0x0f), bs8(0x54), no_xmm_pref] + rmmod(xmm_reg, rm_arg_xmm))
3862 addop("andpd", [bs8(0x0f), bs8(0x54), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3863 
3864 ## OR
3865 addop("orps", [bs8(0x0f), bs8(0x56), no_xmm_pref] + rmmod(xmm_reg, rm_arg_xmm))
3866 addop("orpd", [bs8(0x0f), bs8(0x56), pref_66] + rmmod(xmm_reg, rm_arg_xmm))
3867 
3868 ## AND
3869 # MMX
3870 addop("pand", [bs8(0x0f), bs8(0xdb), no_xmm_pref] +
3871  rmmod(mm_reg, rm_arg_mm), [mm_reg, rm_arg_mm])
3872 # SSE
3873 addop("pand", [bs8(0x0f), bs8(0xdb), pref_66] +
3874  rmmod(xmm_reg, rm_arg_xmm), [xmm_reg, rm_arg_xmm])
3875 
3876 ## OR
3877 # MMX
3878 addop("por", [bs8(0x0f), bs8(0xeb), no_xmm_pref] +
3879  rmmod(mm_reg, rm_arg_mm), [mm_reg, rm_arg_mm])
3880 # SSE
3881 addop("por", [bs8(0x0f), bs8(0xeb), pref_66] +
3882  rmmod(xmm_reg, rm_arg_xmm), [xmm_reg, rm_arg_xmm])
3883 
3884 ## XOR
3885 # MMX
3886 addop("pxor", [bs8(0x0f), bs8(0xef), no_xmm_pref] +
3887  rmmod(mm_reg, rm_arg_mm))
3888 # MMX
3889 addop("pxor", [bs8(0x0f), bs8(0xef), pref_66] +
3890  rmmod(xmm_reg, rm_arg_xmm))
3891 
3892 ### Convert
3893 ### SS = single precision
3894 ### SD = double precision
3895 ###
3896 
3897 ## SS -> SD
3898 ##
3899 
3900 addop("cvtdq2pd", [bs8(0x0f), bs8(0xe6), pref_f3]
3901  + rmmod(xmm_reg, rm_arg_xmm_m64))
3902 addop("cvtdq2ps", [bs8(0x0f), bs8(0x5b), no_xmm_pref]
3903  + rmmod(xmm_reg, rm_arg_xmm))
3904 addop("cvtpd2dq", [bs8(0x0f), bs8(0xe6), pref_f2]
3905  + rmmod(xmm_reg, rm_arg_xmm))
3906 addop("cvtpd2pi", [bs8(0x0f), bs8(0x2d), pref_66]
3907  + rmmod(mm_reg, rm_arg_xmm))
3908 addop("cvtpd2ps", [bs8(0x0f), bs8(0x5a), pref_66]
3909  + rmmod(xmm_reg, rm_arg_xmm))
3910 addop("cvtpi2pd", [bs8(0x0f), bs8(0x2a), pref_66]
3911  + rmmod(xmm_reg, rm_arg_mm_m64))
3912 addop("cvtpi2ps", [bs8(0x0f), bs8(0x2a), no_xmm_pref]
3913  + rmmod(xmm_reg, rm_arg_mm_m64))
3914 addop("cvtps2dq", [bs8(0x0f), bs8(0x5b), pref_66]
3915  + rmmod(xmm_reg, rm_arg_xmm))
3916 addop("cvtps2pd", [bs8(0x0f), bs8(0x5a), no_xmm_pref]
3917  + rmmod(xmm_reg, rm_arg_xmm_m64))
3918 addop("cvtps2pi", [bs8(0x0f), bs8(0x2d), no_xmm_pref]
3919  + rmmod(mm_reg, rm_arg_xmm_m64))
3920 addop("cvtsd2si", [bs8(0x0f), bs8(0x2d), pref_f2]
3921  + rmmod(reg, rm_arg_xmm_m64))
3922 addop("cvtsd2ss", [bs8(0x0f), bs8(0x5a), pref_f2]
3923  + rmmod(xmm_reg, rm_arg_xmm_m64))
3924 addop("cvtsi2sd", [bs8(0x0f), bs8(0x2a), pref_f2]
3925  + rmmod(xmm_reg, rm_arg))
3926 addop("cvtsi2ss", [bs8(0x0f), bs8(0x2a), xmmreg, pref_f3]
3927  + rmmod(xmm_reg, rm_arg))
3928 addop("cvtss2sd", [bs8(0x0f), bs8(0x5a), pref_f3]
3929  + rmmod(xmm_reg, rm_arg_xmm_m32))
3930 addop("cvtss2si", [bs8(0x0f), bs8(0x2d), pref_f3]
3931  + rmmod(rmreg, rm_arg_xmm_m32))
3932 addop("cvttpd2pi",[bs8(0x0f), bs8(0x2c), pref_66]
3933  + rmmod(mm_reg, rm_arg_xmm))
3934 addop("cvttpd2dq",[bs8(0x0f), bs8(0xe6), pref_66]
3935  + rmmod(xmm_reg, rm_arg_xmm))
3936 addop("cvttps2dq",[bs8(0x0f), bs8(0x5b), pref_f3]
3937  + rmmod(xmm_reg, rm_arg_xmm))
3938 addop("cvttps2pi",[bs8(0x0f), bs8(0x2c), no_xmm_pref]
3939  + rmmod(mm_reg, rm_arg_xmm_m64))
3940 addop("cvttsd2si",[bs8(0x0f), bs8(0x2c), pref_f2]
3941  + rmmod(reg, rm_arg_xmm_m64))
3942 addop("cvttss2si",[bs8(0x0f), bs8(0x2c), pref_f3]
3943  + rmmod(reg, rm_arg_xmm_m32))
3944 
3945 
3946 mn_x86.bintree = factor_one_bit(mn_x86.bintree)
3947 # mn_x86.bintree = factor_fields_all(mn_x86.bintree)
3948 """
3949 mod reg r/m
3950  XX XXX XXX
3951 
3952 """
3953 
3954 
3955 def print_size(e):
3956  print e, e.size
3957  return e
def parse_deref_regreg
Definition: arch.py:164
def getfieldindexby_name
Definition: cpu.py:846
def gen_base_expr
Definition: cpu.py:309
def parse_deref_regregint
Definition: arch.py:169
def swap_uint
Definition: cpu.py:1578
def parse_deref_intmreg
Definition: arch.py:194
def print_size
MMX/SSE/AVX operations  Categories are the same than here: https://software.intel.com/sites/landingpage/IntrinsicsGuide/.
Definition: arch.py:3955
def parse_deref_regint
Definition: arch.py:157
def parse_deref_segmoff
Definition: arch.py:218
def factor_one_bit
Definition: cpu.py:712
def parse_deref_reg_intmreg_int
Definition: arch.py:185
def swap_sint
Definition: cpu.py:1590
def sign_ext
Definition: cpu.py:1602
def parse_deref_intmregint
Definition: arch.py:201
def parse_deref_reg_intmreg
Definition: arch.py:177